Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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ATM Pace Control
MPC885 PowerQUICC Family Reference Manual, Rev. 2
40-16 Freescale Semiconductor
0x0A ETQEND
3
Half
Word
Enhanced Transmit Queue End pointer UD
0x0C ETQAPTR
3
Half
Word
Enhanced Transmit Queue- APC pointer ETQBASE
0x0E ETQTPTR
3
Half
Word
Enhanced Transmit Queue- Transmitter
Pointer ETQBASE
0x10 APC_MI Half
Word
APC—Max iteration User defined
0x12 NCITS Half
Word
Number of cells in time slot. See Table 40-2 . User defined
0x14 APCNT Half
Word
APC—N timer 0000
0x16 — Reserved -
0x18 EAPCST1
3
Half
Word
ESAR APC state for the first priority service User defined.
0x1A PTP_COUNTER Half
Word
First priority PTP queue length. 0000.
0x1C PTP_TxCh Half
Word
First priority PTP channel User defined.
0x1E Reserved — — —
4
… … … … …
(n * 0x20) + 0x0 APCT_BASEn Half
Word
APC scheduling table base pointer for the N’th
priority APC level User defined
(n * 0x20) + 0x2 APCT_ENDn Half
Word
N’th table —Length User defined
(n * 0x20) + 0x4 APCT_PTRn Half
Word
N’th APC scheduling table pointer APCT_BASEn value
(n * 0x20) + 0x6 APCT_SPTRn Half
Word
N’th table APC service pointer APCT_BASEn value‘
(n * 0x20) + 0x8–
(n * 0x20) + 0x17 Reserved — — —
(n * 0x20) + 0x18 EAPCSTn Half
Word
APC state for the N’th priority service User defined.
(n * 0x20) + 0x1A PTP_COUNTERn Half
Word
N’th priority PTP queue length. 0000
(n * 0x20) + 0x1C PTP_TxChn Half
Word
N’th priority PTP channel User defined.
Table 40-1. APC Priority Levels (continued)
Offset
1 2
Name Width Description User Writes