System Development and Debugging
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
53-21
time is long because of a large resistor, the setup time for debug port signals should be adjusted
accordingly.
When debug mode is disabled, all development support registers are accessible when MSR[PR]
= 0 and
can be used by monitor debugger software. However, the processor never enters debug mode and the ICR
and DER are used only for asserting and negating the freeze signal. For more information on the software
monitor debugger support, see
Section 53.4, “Software Monitor Debugger Support.”
All development
support registers accessible only when the core is in debug mode; therefore, the development system has
full control of the core’s development support features. For more information, see
Table 53-15
. If debug
mode is enabled as described in this section, debug mode can be entered by the methods described in
Section 53.3.1.2, “Entering Debug Mode.”
53.3.1.2
Entering Debug Mode
By appropriately programming the development port during reset, debug mode can be entered
immediately out of reset, thus allowing the user to debug a ROM-less system. If DSCK is asserted
throughout SRESET assertion and then past SRESET negation, the processor takes a breakpoint exception
and goes directly to debug mode instead of fetching the reset vector.
To avoid entering debug mode after reset, DSCK must be negated no later than seven clock cycles after
SRESET negates, allowing the processor to jump to the reset vector and begin normal execution. If debug
mode is entered immediately after reset, as shown in
Figure 53-7
, ICR[DPI] is set.
The user can enable events that can initiate debug mode and determine which events require regular
interrupt handling.
The following events can cause the core to enter debug mode. Each event results in debug mode entry if
debug mode is enabled and the corresponding enable bit is set in the DER. The reset values of the enable
bits allow use of the debug mode features without programming the DER in most cases. See
Table 53-25
.
•
System reset, as a result of the assertion of SRESET, as described in
Section 6.1.2.1, “System Reset
Interrupt (0x00100)”
•
Checkstop, as described in
Table 53-9
•
Machine check interrupt
•
Implementation-specific ITLB miss
•
Implementation-specific ITLB error
•
Implementation-specific DTLB miss
•
Implementation-specific DTLB error
•
External interrupt, recognized when MSR[EE] = 1
•
Alignment exception
•
Program exception
•
Floating-point unavailable exception
•
Decrementer interrupt, recognized when MSR[EE] = 1
•
System call exception
Summary of Contents for PowerQUICC MPC870
Page 98: ...MPC885 PowerQUICC Family Reference Manual Rev 2 I 4 Freescale Semiconductor ...
Page 118: ...MPC885 Overview MPC885 PowerQUICC Family Reference Manual Rev 2 1 20 Freescale Semiconductor ...
Page 158: ...The MPC8xx Core MPC885 PowerQUICC Family Reference Manual Rev 2 3 18 Freescale Semiconductor ...
Page 288: ...MPC885 PowerQUICC Family Reference Manual Rev 2 III 4 Freescale Semiconductor ...
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Page 1090: ...UTOPIA Interface MPC885 PowerQUICC Family Reference Manual Rev 2 43 8 Freescale Semiconductor ...
Page 1312: ...Byte Ordering MPC885 PowerQUICC Family Reference Manual Rev 2 A 8 Freescale Semiconductor ...
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Page 1370: ...MPC880 MPC885 PowerQUICC Family Reference Manual Rev 2 E 4 Freescale Semiconductor ...
Page 1386: ...Revision History MPC885 PowerQUICC Family Reference Manual Rev 2 I 2 Freescale Semiconductor ...