Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Clocks and Power Control
MPC885 PowerQUICC Family Reference Manual, Rev. 2
14-18 Freescale Semiconductor
The following event cause the MPC885 to leave normal low mode and enter normal high mode:
• The communications processor (CP) has a service request from a peripheral (SCC, SMC, etc.).
This option is maskable with SCCR[CRQEN].
14.6 Clock and Power Control Registers
The following sections describe the clock and power control registers.
14.6.1 System Clock and Reset Control Register (SCCR)
The DPLL has a 32-bit control register, the system clock and reset control register (SCCR), shown in
Figure 14-12 , which is memory-mapped into the MPC885 SIU’s register map.
0 1 2 3 5 6 7 8 9 10 11 12 13 14 15
Field — COM — TBS PTDIV PTSEL CRQEN – — EBDF —
HRESET — # 0 # # # 0 0 0 † 0
POR 0 0 0 0 * * 0 0 0 † 0
R/W R/W
Addr (IMMR & 0xFFFF0000) + 280
16 17 18 19 20 21 23 24 26 27 29 30 31
Field — DFSYNC DFBRG DFNL DFNH DFUTP DFAUTP
HRESET 0
POR 0
R/W R/W
Addr (IMMR & 0xFFFF0000) + 282
Note: HRESET is hard reset and POR is power-on reset.
# The field is undefined
— The field is unaffected.
*
PTDIV depends on the combination of MODCK1 and MODCK2. PTSEL depends on MODCK1. See Table 14-5 for
more information.
† This field is set according to the default of the hard reset configuration word.
Figure 14-12. System Clock and Reset Control Register (SCCR)