Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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System Interface Unit
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 10-25
10.9.3 Timebase Status and Control Register (TBSCR)
The timebase status and control register (TBSCR) controls the timebase count enable and interrupt
generation. It is also used for reporting the interrupt sources, and it can be read at any time. Status bits are
cleared by writing ones; writing zeros has no effect. Note that TBSCR is a keyed register. It must be
unlocked in TBSCRK before it can be written.
This register is affected by HRESET but is not affected by SRESET. Table 10-19 describes TBSCR fields.
10.10 Periodic Interrupt Timer (PIT)
The PIT, shown in Figure 10-23 , consists of a 16-bit counter clocked by a PITCLK clock supplied by the
clock module. The PIT is not affected by HRESET and RESET; however, it is disabled and reset by
PORESET. It decrements to zero when loaded with a value from the PIT count register (PITC) and after
the timer reaches zero, PS is set and an interrupt is generated if PIE is a 1. At the next input clock edge,
the PITC value is loaded into the counter and the process repeats. When a new value is loaded into PITC,
the PIT is updated, the divider is reset, and the counter starts counting. If the PS bit is set, an interrupt is
generated at the interrupt controller that remains pending until PS is cleared. If PS is set again, before being
cleared, the interrupt remains pending until PS is cleared. Any write to PITC stops the current countdown
0 7 8 9 10 11 12 13 14 15
Field TBIRQ REFA REFB — REFAE REFBE TBF TBE
Reset 0000_0000_0000_0000
R/W R/W
Addr (IMMR & 0xFFFF0000) + 0x200
Figure 10-22. Timebase Status and Control Register (TBSCR)
Table 10-19. TBSCR Field Descriptions
Bits Name Description
0–7 TBIRQ Timebase interrupt request. Determines interrupt priority level of the timebase. To specify a
certain level, the appropriate bit should be set.
8 REFA Reference interrupt status. If set, indicates that a match was detected between the
corresponding reference register (TBREFA for REFA and TBREFB for REFB) and the TBL.
REFA and REFB are cleared by writing ones.
9 REFB
10–11 — Reserved, should be cleared.
12 REFAE Reference interrupt enable. If asserted, the timebase generates an interrupt on assertion of
REFA or REFB. Otherwise, the interrupt is disabled.
13 REFBE
14 TBF Timebase freeze enable
0 The timebase and decrementer are unaffected.
1 The FRZ signal stops the timebase and decrementer.
15 TBE Timebase enable
0 Disables timebase and decrementer operation.
1 Enables timebase and decrementer operation.