Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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SCC BISYNC Mode
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 26-9
pattern. Unless SYNL is zero (external sync), the transmitter always sends the entire DSR contents, lsb
first, before each frame—the chosen 4- or 8-bit pattern can be repeated in the lower-order bits.
26.10 Handling Errors in the SCC BISYNC
The controller reports message transmit and receive errors using the channel BDs, error counters, and the
SCCE. Modem lines can be directly monitored via the port C pins.
Table 26-8 describes transmit errors.
Table 26-9 describes receive errors.
Table 26-7. Receiver SYNC Pattern Lengths of the DSR
GSMR_H[SYNL]
Setting
Bit Assignments
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
00 An external SYNC signal is used instead of the SYNC pattern in the DSR.
01 4-Bit
10 8-Bit
11 16-Bit
Table 26-8.
Transmit Errors
Error Description
Transmitter
Underrun
The channel stops sending the buffer, closes it, sets TxBD[UN], and generates a TXE interrupt if it
is enabled. The channel resumes transmission after a
RESTART TRANSMIT
command is received.
Underrun cannot occur between frames or during a DLE–XXX pair in transparent mode.
CTS Lost during
Message
Transmission
The channel stops sending the buffer, closes it, sets TxBD[CT], and generates a TXE interrupt if not
masked. Transmission resumes when a
RESTART TRANSMIT
command is received.
Table 26-9.
Receive Errors
Error Description
Overrun The controller maintains a receiver FIFO for receiving data. The CP begins programming the SDMA
channel (if the buffer is in external memory) and updating the CRC when the first byte is received in
the Rx FIFO. If an Rx FIFO overrun occurs, the controller writes the received byte over the previously
received byte. The previous character and its status bits are lost. The channel then closes the buffer,
sets RxBD[OV], and generates the RXB interrupt if it is enabled. Finally, the receiver enters hunt
mode.
CD Lost during
Message
Reception
The channel stops receiving, closes the buffer, sets RxBD[CD], and generates the RXB interrupt if
not masked. This error has the highest priority. If the rest of the message is lost, no other errors are
checked in the message. The receiver immediately enters hunt mode.
Parity The channel writes the received character to the buffer and sets RxBD[PR]. The channel stops
receiving, closes the buffer, sets RxBD[PR], and generates the RXB interrupt if it is enabled. The
channel also increments PAREC and the receiver immediately enters hunt mode.
CRC The channel updates the CR bit in the BD every time a character is received with a byte delay of
eight serial clocks between the status update and the CRC calculation. When control character
recognition is used to detect the end of the block and cause CRC checking, the channel closes the
buffer, sets the CR bit in the BD, and generates the RXB interrupt if it is enabled.