Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Parallel I/O Ports
MPC885 PowerQUICC Family Reference Manual, Rev. 2
34-4 Freescale Semiconductor
This register is affected by HRESET but is not affected by SRESET. Table 34-2 describes PAODR bits.
34.2.1.2 Port A Data Register (PADAT)
Reading the port A data (PADAT) register returns the value of the signal, regardless of whether the signal
is an input or output. Comparing written data with the data on the signal can detect output conflicts. A write
to a PADAT bit is latched; if the bit is configured as an output, the value latched for that bit is driven onto
its respective signal. PADAT can be read or written at any time, is not initialized, and is undefined at reset.
This register is not affected by HRESET or SRESET. Table 34-3 describes PADAT bits.
34.2.1.3 Port A Data Direction Register (PADIR)
Port A data direction register (PADIR) bits configure port A signals as general-purpose inputs or outputs.
If a signal is not programmed for general-purpose I/O, PADIR selects the peripheral function to be
performed.
0 7 8 9 10 11 12 13 14 15
Field — OD8 OD9 OD10 OD11 OD12 — OD14 —
Reset 0
R/W R/W
Addr 0x954
Figure 34-1. Port A Open-Drain Register (PAODR)
Table 34-2. PAODR Bit Descriptions
Bits Name Description
0–7, 13, 15 — Reserved, should be cleared.
8–12, 14 OD n Tells how the corresponding port A signal is interpreted.
0 The signal is actively driven as an output.
1 The signal is an open-drain driver. Outputs are actively driven low. Otherwise, it is
three-stated.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Addr 0x956
Figure 34-2. Port A Data Register (PADAT)
Table 34-3. PADAT Bit Descriptions
Bits Name Description
0–15 D n Contains the data on the corresponding signal