Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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MPC8xx Core Register Set
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 4-11
4.1.3.1 Accessing SPRs
All SPRs are accessed using the mtspr and mfspr instructions, regardless of whether they are within the
processor core. To access registers outside of the core, an internal bus tenure occurs using the address lines,
as described in
Table 4-11 .
Address errors in this tenure cause a software emulation exception.
149 00100 10101 DER Fetch sync on write
150 00100 10110 COUNTA Fetch sync on write
151 00100 10111 COUNTB Fetch sync on write
152 00100 11000 CMPE Write: Fetch sync
Read: Sync relative to load/store operations
153 00100 11001 CMPF Write: Fetch sync
Read: Sync relative to load/store operations
154 00100 11010 CMPG Write: Fetch sync
Read: Sync relative to load/store operations
155 00100 11011 CMPH Write: Fetch sync
Read: Sync relative to load/store operations
156 00100 11100 LCTRL1 Write: Fetch sync
Read: Sync relative to load/store operations
157 00100 11101 LCTRL2 Write: Fetch sync
Read: Sync relative to load/store operations
158 00100 11110 ICTRL Fetch sync on write
159 00100 11111 BAR Write: Fetch sync
Read: Sync relative to load/store operations. See
Section 4.1.2.1, “DAR, DSISR, and BAR Operation.”
630 10011 10110 DPDR Read and Write
Table 4-11. Addresses of SPRs Located Outside of the Core
Address Lines
0:17 18:22 23:27 28:31
0...0 SPR[0–4] SPR[5–9] 0000
Table 4-10. MPC885-Specific Debug-Level SPRs (continued)
SPR Number
Name Serialize Access
Decimal SPR[5–9] SPR[0–4]