Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Memory Map
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 2-3
134 OR6—Option register bank 6 32 bits 15.4.2/15-11
138 BR7—Base register bank 7 32 bits 15.4.1/15-8
13C OR7—Option register bank 7 32 bits 15.4.2/15-11
140–163 Reserved 36 bytes —
164 MAR—Memory address register 32 bits 15.4.7/15-17
168 MCR—Memory command register 32 bits 15.4.5/15-15
16C–16F Reserved 4 bytes —
170 MAMR—Machine A mode register 32 bits 15.4.4/15-14
174 MBMR—Machine B mode register 32 bits 15.4.4/15-14
178 MSTAT—Memory status register 16 bits 15.4.3/15-13
17A MPTPR—Memory periodic timer prescaler 16 bits 15.4.8/15-18
17C MDR—Memory data register 32 bits 15.4.6/15-17
180–1FF Reserved 128 bytes —
System Integration Timers
200 TBSCR—Timebase status and control register 16 bits 10.9.3/10-25
202–203 Reserved 2 bytes —
204 TBREFA—Timebase reference register A 32 bits 10.9.2/10-24
208 TBREFB—Timebase reference register B 32 bits
20C–21F Reserved 20 bytes —
220 Reserved 16 bits —
222–223 Reserved 2 bytes —
224 Reserved 32 bits —
228 Reserved 32 bits —
22C Reserved 32 bits —
230–23F Reserved 16 bytes —
240 PISCR—Periodic interrupt status and control register 16 bits 10.10.1/10-26
242–243 Reserved 2 bytes —
244 PITC—Periodic interrupt count registerA 32 bits 10.10.2/10-27
248 PITR—Periodic interrupt timer register 32 bits 10.10.3/10-28
24C–27F Reserved 52 bytes —
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset Name Size Section/Page