Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 11-1
Chapter 11
Reset
The reset block has reset control logic that determines the cause of reset, synchronizes it if necessary, and
resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller,
and parallel I/O signals are initialized only on hard reset. Soft reset initializes the internal logic while
maintaining the system configuration. The system configuration includes the SIU pin configuration, the
parallel I/O configuration, and the memory controller configuration.
Table 11-1 shows the reset responses
of the MPC885.
11.1 Types of Reset
The MPC885 has several sources of input to the reset logic:
• Power-on reset
• External hard reset
• Internal hard reset
— Software watchdog reset
— Checkstop reset
— Debug port hard reset
• JTAG reset
Table 11-1. MPC885 Reset Responses
Reset Source
Reset Effect
Reset Logic
and PLL
States Reset
System
Configuration
1
Reset
1
Includes SIU pin configuration, the parallel I/O configuration and the memory controller configuration
Clock
Module
Reset
HRESET
Driven
Debug
Port
Config
Other Internal
Logic
2
Config
Reset
2
Includes all other CPM and core logic not explicitly noted elsewhere in the table
SRESET
Driven
Power-on reset Yes Yes Yes Yes Yes Yes Yes
External hard
reset,
loss-of-lock,
software
watchdog,
checkstop, debug
port hard reset No
JTAG reset,
external soft
reset, debug port
soft reset No No No