Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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SEC Lite Controller
MPC885 PowerQUICC Family Reference Manual, Rev. 2
51-2 Freescale Semiconductor
Figure 51-1. Interrupt Mask Register 1
Figure 51-2 shows the bit positions of potential interrupt source indicated in Interrupt Mask Register 2.
A complete definition of the bits that can be masked by the Interrupt Mask Registers is shown in
Table 51-1 and Table 51-2 .
Figure 51-2. Interrupt Mask Register 2
51.1.2 Interrupt Status Registers
The ISR contains fields representing all possible sources of interrupts. The Interrupt Status Registers are
cleared either by a reset, or by writing the appropriate bits active in the Interrupt Clear Register.
Figure 51-3 shows the bit positions of potential interrupt sources indicated in Interrupt Status Register 1.
0 1 2 3 4 15
Field CHA —
Definition Err Dn
Reset 0x0000
R/W R/W
Addr 0x 01008
16 31
Field —
Definition
Reset 0x0000
R/W R/W
Addr 0x 01008
0 14 15
Field — MDEU
Definition Err Dn
Reset 0x0000
R/W R/W
Addr 0x 0100C
16 17 18 19 20 21 22 23 24 25 26 31
Field — AESU — DEU — TEA —
Definition Err Dn Err Dn
Reset 0x0000
R/W R/W
Addr 0x 0100C