Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 52-1
Chapter 52
SEC Lite Master/Slave Interface Module
52.1 Communications Processor Timing Register (CPTR)
The CPTR contains seven bits for the SEC Lite interface.
Table 52-1 describes the CPTR[16–22] SEC Lite–related bits. CPTR[23–28], the RMII bits, are described
in Section 45.3.1, “Communications Processor Timing Register (CPTR).”
0 15
Field —
Reset 0000_0000
R/W Read/Write
Addr 0x0ADC
16 18 19 20 22 23 24 25 26 27 28 29 30 31
Field SEC_INT SEC_BO SEC_AT1–AT3 FEC1 FEC2 1TCI 2TCI RE1 RE2 —
Reset 0000_0000
R/W Read/Write
Addr 0x0ADE
Figure 52-1. CPTR Register
Table 52-1. CPTR SEC Lite–Related Field Descriptions
Bits Name Description
0–15 — Reserved, should be cleared.
16–18 SEC_INT SEC Lite Interrupt Level
000 Level 0
001 Level 1
010 Level 2
011 Level 3
100 Level 4
101 Level 5
110 Level 6
111 Level 7
19 SEC_BO SEC Lite Byte Order
0 Big endian
1 Little endian
20–22 SEC_AT1–AT3 SEC Lite Address Type AT1–3—the function code used during bus access (AT0 is
driven with a 1 to identify a DMA type access)