Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Parallel I/O Ports
MPC885 PowerQUICC Family Reference Manual, Rev. 2
34-18 Freescale Semiconductor
Port D includes the UTOPIA data and control signals. When PDPAR[UT] is set, most of the port D signals
are configured to support UTOPIA signals as shown in the table below. The UTOPIA interface is described
in the chapter, "UTOPIA Interface".
Table 34-18 shows defaults for port D signal options.
Port D includes the UTOPIA data and control signals. When PDPAR[UT] is set, most of the port D signals
are configured to support UTOPIA signals as shown in
Table 43-2 . The UTOPIA interface is described in
Chapter 43, “UTOPIA Interface.”
Port D also includes the Media Independent Interface signals. When PDPAR[UT] is cleared, the MII
functionality can be invoked by setting the PDDIR =1. The Fast Ethernet Controller is described in
Chapter 45, “Fast Ethernet Controller (FEC).”
34.5.1 Port D Registers
Port D has three memory-mapped, read/write control registers.
34.5.1.1 Port D Data Register
A read of the port D data (PDDAT) register returns the value of the signal, regardless of whether it is an
input or output. This allows output conflicts to be found on the signal by comparing the written data with
Table 34-18. Port D Pin Assignment
Signal PDPAR = 0
PDPAR=1
Input to On-Chip
Peripherals
UT=0 UT=1
PDDIR=0 PDDIR=1 PDDIR=0 PDDIR=1
PD15 Port D15 L1TSYNCA — UTPB[0] L1TSYNCA=GND
PD14 Port D14 L1RSYNCA — UTPB[1] L1RSYNCA=GND
PD13 Port D13 L1TSYNCB — UTPB[2] L1TSYNCB=GND
PD12 Port D12 L1RSYNCB — UTPB[3] L1RSYNCB=GND
PD11 Port D11 RXD3 — RxEnb RXD3 = PA9
PD10 Port D10 TXD3 — TxEnb —
PD9 Port D9 — TXD4 UtpClk —
PD8 Port D8 MII-MDC
RMII-MDC
RXD4 MII-MDC
RMII-MDC
— RXD4 = PA11
PD7 Port D7 RTS3 — UTPB[4] —
PD6 Port D6 RTS4 — UTPB[5] —
PD5 Port D5 CLK8/
L1TCLKB
— UTPB[6] CLK8/ L1TCLKB = GND
PD4 Port D4 CLK4 — UTPB[7] CLK4 = BRG03
PD3 Port D3 CLK7/TIN4 — SOC CLK7/TIN4 = PA10