Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Memory Controller
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 15-39
2 CST2 Chip-select timing 2. Defines the state of CS during clock phase 3.
0 Asserted at the rising edge of GCLK2_50.
1 Negated at the rising edge of GCLK2_50.
3 CST3 Chip-select timing3. Defines the state of CS during clock phase 4.
0 Asserted at the falling edge of GCLK1_50.
1 Negated at the falling edge of GCLK1_50.
4 BST4 Byte-select timing 4. Defines the state of BS during clock phase 1.
0 Asserted at the falling edge of GCLK2_50.
1 Negated at the falling edge of GCLK2_50.
The final value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30:31] for
the access. See
Section 15.6.4.3, “Byte-Select Signals (BSTx).”
5 BST1 Byte-select timing 1. Defines the state of BS during clock phase 2.
0 Asserted at the rising edge of GCLK1_50.
1 Negated at the rising edge of GCLK1_50.
The final value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30:31] for
the access. See
Section 15.6.4.3, “Byte-Select Signals (BSTx).”
6 BST2 Byte-select timing 2. Defines the state of BS during clock phase 3.
0 Asserted at the rising edge of GCLK2_50.
1 Negated at the rising edge of GCLK2_50
The final value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30:31] for
the access. See
Section 15.6.4.3, “Byte-Select Signals (BSTx).”
7 BST3 Byte-select timing 3. Defines the state of BS during clock phase 4.
0 Asserted at the falling edge of GCLK1_50.
1 Negated at the falling edge of GCLK1_50.
The final value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30:31] for
the access. See
Section 15.6.4.3, “Byte-Select Signals (BSTx).”
8–9 G0L General-purpose line 0 lower. Defines the state of GPL0 during phases 1–3.
10 Asserted at the falling edge of GCLK2_50.
11 Negated at the falling edge of GCLK2_50.
00 Driven at the falling edge of GCLK2_50 with an address signal as defined in M
xMR[G0CLx].
10–11 G0H General-purpose line 0 higher. Defines the state of GPL0 during phase 4.
10 Asserted at the falling edge of GCLK1_50.
11 Negated at the falling edge of GCLK1_50.
00 Driven at the falling edge of GCLK1_50 with an address signal as defined in M
xMR[G0CLx].
12 G1T4 General-purpose line 1 timing 4. Defines the state of GPL1 during phase 1–3.
0 Asserted at the falling edge of GCLK2_50.
1 Negated at the falling edge of GCLK2_50.
13 G1T3 General-purpose line 1 timing 3. Defines the state of GPL1 during phase 4.
0 Asserted at the falling edge of GCLK1_50.
1 Negated at the falling edge of GCLK1_50.
14 G2T4 General-purpose line 2 timing 4. Defines the state of GPL2 during phase 1–3.
0 Asserted at the falling edge of GCLK2_50.
1 Negated at the falling edge of GCLK2_50.
15 G2T3 General-purpose line 2 timing 3. Defines the state of GPL2 during phase 4.
0 Asserted at the falling edge of GCLK1_50.
1 Negated at the falling edge of GCLK1_50.
Table 15-14. RAM Word Bit Settings (continued)
Bit Name Description