Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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MPC885 Instruction Set
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 5-11
5.2.4.2 Load and Store Instructions
Load and store instructions are issued and translated in program order; however, the accesses can occur
out of order. Synchronizing instructions are provided to enforce strict ordering. This section describes the
load and store instructions of the MPC885, which consist of the following:
• Integer load instructions
• Integer store instructions
• Integer load and store with byte-reverse instructions
• Integer load and store multiple instructions
• Integer load and store string instructions
5.2.4.2.1 Integer Load and Store Address Generation
Integer load and store operations generate effective addresses using register indirect with immediate index
mode, register indirect with index mode, or register indirect mode. See
Section 5.2.2.2, “Effective Address
Calculation,” for information about calculating effective addresses. Note that the MPC885 is optimized for
load and store operations that are aligned on natural boundaries, and operations that are not naturally
aligned may suffer performance degradation. Refer to
Section 6.1.2.6.1, “Integer Alignment Exceptions,”
for additional information about load and store address alignment exceptions.
5.2.4.2.2 Register Indirect Integer Load Instructions
For integer load instructions, the byte, half word, or word addressed by the EA is loaded into rD. Many
integer load instructions have an update form, in which rA is updated with the generated effective address.
For these forms, the EA is placed into rA and the memory element (byte, half word, word, or double word)
addressed by EA is loaded into rD.
Table 5-7 lists the integer load instructions.
Table 5-7. Integer Load Instructions
Name Mnemonic Syntax
Load Byte and Zero lbz r D,d( r A)
Load Byte and Zero Indexed lbzx r D, r A, r B
Load Byte and Zero with Update lbzu r D,d( r A)
Load Byte and Zero with Update Indexed lbzux r D, r A, r B
Load Half Word and Zero lhz r D,d( r A)
Load Half Word and Zero Indexed lhzx r D, r A, r B
Load Half Word and Zero with Update lhzu r D,d( r A)
Load Half Word and Zero with Update Indexed lhzux r D, r A, r B
Load Half Word Algebraic lha r D,d( r A)
Load Half Word Algebraic Indexed lhax r D, r A, r B
Load Half Word Algebraic with Update lhau r D,d( r A)
Load Half Word Algebraic with Update Indexed lhaux r D, r A, r B