Freescale Semiconductor PowerQUICC MPC870, Reference Manual

Page: 419 / 1426

Clocks and Power Control
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 14-3
14.2 Clock Module
The clock module consists of two external reference sources and a programmable phase-locked loop,
arranged as shown in
Figure 14-2 .
Figure 14-2. Clock Module Components
14.2.1 External Reference Clocks
The MPC885 has two input clock sources, provided at the EXTCLK pin or at the EXTAL and XTAL pins.
These two clock sources can select to drive three internal clock signals, referred to as OSCLK, PITCLK,
and TMBCLK. OSCLK provides the input clock to the phase-locked loop. PITCLK and TMBCLK
provide dedicated clocks for special system timer circuitry, which includes the periodic interrupt timer
(PIT), timebase (TB), and decrementer (DEC) in the SIU. These separate clock sources for the PIT, TB,
and DEC are provided to enable these modules to continue to count at a fixed, user-defined rate regardless
of system frequency.
The clock sources for OSCLK, PITCLK, and TMBCLK are selected at reset. The sources for PITCLK and
TMBCLK can also be selected in software by manipulation of SCCR; see
Section 14.6.1, “System Clock
and Reset Control Register (SCCR).” For more information, see Section 14.2.3, “DPLL Reset
Configuration,” Section 14.3.2, “PIT Clock (PITCLK),” and Section 14.3.3, “Time Base and Decrementer
Clock (TMBCLK).”
EXTAL XTAL
OSCM
Crystal = 10 MHz
DPLL and Interface Logic
OSC
CLKOUT
EXTCLK
VSSSYN
0.1uF
0.1uF
GND
VDD
V
SSSYN1
V
DDSYN
CKPLPDM
Low-Power Divider
2:1
MUX