Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Memory Map
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 2-7
9AE TCN4—Timer 4 counter 16 bits 17.2.4.3/17-10
9B0 TER1—Timer 1 event register 16 bits 17.2.4.4/17-11
9B2 TER2—Timer 2 event register 16 bits 17.2.4.4/17-11
9B4 TER3—Timer 3 event register 16 bits 17.2.4.4/17-11
9B6 TER4—Timer 4 event register 16 bits 17.2.4.4/17-11
9B8–9BF Reserved 8 bytes —
Communications Processor (CP)
9C0 CPCR—CP command register 16 bits 18.6.3/18-7
9C2–9C3 Reserved 2 bytes —
9C4 RCCR—RISC controller configuration register 16 bits 18.6.1/18-5
9C6 Reserved 8 bits —
9C7 RMDS—RISC microcode development support
control register 8 bits 18.6.2/18-6
9C8–9CB Reserved 4 bytes —
9CC RCTR1—RISC controller trap register 1 16 bits Used only by optional RAM
microcode
9CE RCTR2—RISC controller trap register 2 16 bits Used only by optional RAM
microcode
9D0 RCTR3—RISC controller trap register 3 16 bits Used only by optional RAM
microcode
9D2 RCTR4—RISC controller trap register 4 16 bits Used only by optional RAM
microcode
9D4–9D5 Reserved 2 bytes —
9D6 RTER—RISC timer event register 16 bits 18.8.4/18-17
9D8–9D9 Reserved 2 bytes —
9DA RTMR—RISC timers mask register 16 bits 18.8.4/18-17
9DC–9EF Reserved 20 bytes —
Baud Rate Generators
9F0 BRGC1—BRG1 configuration register 32 bits 20.4.1/20-37
9F4 BRGC2—BRG2 configuration register 32 bits 20.4.1/20-37
9F8 BRGC3—BRG3 configuration register 32 bits 20.4.1/20-37
9FC BRGC4—BRG4 configuration register 32 bits 20.4.1/20-37
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset Name Size Section/Page