Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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SEC Lite Overview
MPC885 PowerQUICC Family Reference Manual, Rev. 2
46-4 Freescale Semiconductor
• Seven data length/data pointer pairs—The data length indicates the number of contiguous bytes of
data to be transferred. The data pointer indicates the starting address of the data, key, or context in
system memory.
• Next descriptor pointer
A data packet descriptor ends with a pointer to the next data packet descriptor. Upon completion of the
current descriptor, this field is checked and, if non-zero, the channel is instructed to request a burst read of
the next descriptor.
Processing of the next descriptor (and whether or not a done signal is generated) is determined by the
programming of crypto-channel’s configuration register. Two modes of operation are supported:
• Signal done at end of descriptor
• Signal done at end of descriptor chain
The crypto-channel can signal done via an interrupt or by a write-back of the descriptor header after
processing a data packet descriptor. The value written back is identical to that of the header, with the
exception that a DONE field is set.
Occasionally, a descriptor field may not be applicable to the requested service. For example, if using DES
in ECB mode, the contents of the IV field do not affect the result of the DES computation. Therefore, when
processing data packet descriptors, the crypto-channel skips any pointer that has an associated length of
zero.
46.6 Master/Slave Interface
The master/slave interface manages communication between the SEC Lite internal execution units and the
MPC885 internal bus. All on-chip resources are memory mapped, and the target accesses and initiator
writes from the SEC Lite must be addressed on word boundaries. The SEC Lite will perform initiator reads
on byte boundaries and will adjust the data to place on word boundaries as appropriate. Access to system
memory is a critical factor in co-processor performance, and the 32-bit master/slave interface of the SEC
Lite allows it to achieve performance unattainable on secondary busses.
46.7 SEC Lite Controller
The SEC Lite controller manages on-chip resources, including the individual execution units (EUs),
FIFOs, the master/slave interface, and the internal buses that connect all the various modules. The
controller receives service requests from the master/slave interface and the crypto-channel, and schedules
the required activities.
Processing begins when a data packet descriptor pointer is written to the Next Descriptor Pointer Register
of the crypto-channel. Prior to fetching the data referred to by the descriptor and based on the services
requested by the descriptor header in the descriptor buffer, the controller dynamically reserves usage of
the requested EUs to the crypto-channel. Each encryption/decryption packet must contain context that is
particular to the context being supported.