Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Instruction and Data Caches
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 7-27
monitor the internal bus for communication processor module (CPM) accesses of the address associated
with the last lwarx instruction.
If a memory region is marked caching-allowed, the MPC885 assumes that it is the single master in the
system to that region. If a caching-allowed lwarx or stwcx. access misses in the data cache, the transaction
on the internal and external buses do not have a reservation. If the memory region is marked
caching-inhibited or the cache is locked, and the access misses, the lwarx instruction appears on the bus
as a single-beat load with the reservation.
lwarx and stwcx. accesses to write-through memory regions do not generate DSI exceptions. The
MPC885’s data cache treats all stwcx. operations as write-through independent of the memory/cache
access attributes. When the write-through operation completes successfully on the external bus, the data
cache entry is updated (assuming it hits), and CR0[EQ] is modified to reflect the success of the operation.
If the reservation is not intact, the stwcx. cancels the external bus transaction, and the cache block is not
altered.
7.7 Cache Initialization after Reset
At power-on and hard reset, both caches are disabled. Although disabled, the cache state is preserved to
enable the user to investigate the exact state of the cache before the event that caused the reset. To ensure
proper operation after reset, initialize the instruction cache by performing the following:
1. Write the unlock all command (IC_CST[CMD] = 0b101) to the IC_CST register.
2. Write the invalidate all command (IC_CST[CMD] = 0b110) to the IC_CST register.
3. Write the cache enable command (IC_CST[CMD] = 0b001) to the IC_CST register.
Similarly, to ensure proper operation after reset, initialize the data cache by performing the following:
1. Write the unlock all command (DC_CST[CMD] = 0b1010) to the DC_CST register.
2. Write the invalidate all command (DC_CST[CMD] = 0b1100) to the DC_CST register.
3. Write the cache enable command (DC_CST[CMD] = 0b0010) to the DC_CST register.
After the caches are initialized, all the cache blocks are invalidated, and the LRU bits point to way 0 of
each set.
7.8 Debug Support
The MPC885 can be debugged either in debug mode or by a software monitor debugger. In both cases the
core of the MPC885 asserts the internal freeze signal. See
Chapter 53, “System Development and
Debugging,” for a detailed description of the MPC885 debug support.
7.8.1 Instruction and Data Cache Operation in Debug Mode
The development system interface of the MPC885 uses the development port, which is a dedicated serial
port. The development port is a relatively inexpensive interface that allows a development system to
operate in a lower frequency than the core’s frequency and controls system activity when the core is in
debug mode. See
Section 53.3, “Development System Interface,” for more information.