Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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System Development and Debugging
MPC885 PowerQUICC Family Reference Manual, Rev. 2
53-24 Freescale Semiconductor
53.3.2 Development Port Communication
The development port provides a full duplex serial interface for communications between the internal
development support logic and an external development tool.
Figure 53-5 shows the relationship of the
development support logic to the rest of the core. For clarity, the development port support logic is shown
as a separate block.
53.3.2.1 Development Port Pins
The following development port pin functions are provided:
• Development serial clock
• Development serial data in
• Development serial data out
• Freeze
53.3.2.1.1 Development Serial Clock (DSCK)
DSCK is used at reset to enable debug mode, which can be entered either immediately following reset or
for event-driven entry into debug mode as described in
Section 53.3.1.2, “Entering Debug Mode.” The
DSCK input must be driven either high or low at all times and must not be allowed to float. A typical target
environment would pull this input low with a resistor. When the development port is in asynchronous
clocked mode, the development serial clock (DSCK) is used to shift data into and out of the development
port shift register. At the same time, the new msb of the shift register is presented at the DSDO pin.
The clock may be implemented as a free-running or gated clock. As discussed in Section 53.3.2.4,
“Development Port Serial Communications–Trap Enable Mode,” and Section 53.3.2.5, “Development
Port Serial Communications–Debug Mode,” data shifting is controlled by the ready and start signals, so
the clock does not need to be gated with the serial transmissions.
53.3.2.1.2 Development Serial Data In (DSDI)
External logic presents data to be transferred into the development port shift register at the development
serial data in pin (DSDI). When driven asynchronously with the system clock, data presented to DSDI
must be stable at setup time before the rising edge of DSCK and at hold time after the rising edge of DSCK.
When driven synchronously to the system clock, data must be stable on DSDI or a setup time before
system clock output (CLKOUT) rising edge and a hold time after the rising edge of CLKOUT. DSDI is
also used at reset to select the development port clock mode. See
Section 53.3.2.3, “Development Port
Serial Communications–Clock Mode.”
53.3.2.1.3 Development Serial Data Out (DSDO)
Debug mode logic uses the development serial data out pin (DSDO) to shift data out of the development
port shift register. DSDO transitions are synchronous with DSCK or CLKOUT, depending on the clock
mode.