Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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External Signals
MPC885 PowerQUICC Family Reference Manual, Rev. 2
12-32 Freescale Semiconductor
IP_A4 Hi-Z D2 Input Input Port A 4—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
IP_A5 Hi-Z E3 Input Input Port A 5—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface
IP_A6 Hi-Z F4 Bidirectional Input Port A 6—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
IP_A7 Hi-Z C2 Input Input Port A 7—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
ALE_B
DSCK See
Table 12-3
C8 Bidirectional
three-state
Address Latch Enable B—This output is asserted when the
MPC875 initiates an access to a region under the control of the
PCMCIA socket B interface.
Development Serial Clock—This input is the clock for the debug
port interface.
IP_B[0:1]
IWP[0:1]
VFLS[0:1] See
Table 12-3
B8, D9 Bidirectional Input Port B 0-1—The MPC875 senses these inputs; their values
and changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Instruction Watchpoint 0-1—These outputs report the detection of
an instruction watchpoint in the program flow executed by the
core.
Visible History Buffer Flushes Status—The MPC875 outputs
VFLS[0:1] when program instruction flow tracking is required.
They report the number of instructions flushed from the history
buffer in the core.
OP0 Low B6 Output Output Port 0—This output signal is generated by the MPC875 as
a result of a write to the PGCRA register in the PCMCIA interface.
OP1 Low C6 Output Output Port 1—The MPC875 generates these outputs as a result
of a write to the PGCRA register in the PCMCIA interface.
OP2
MODCK1
STS Hi-Z B5 Bidirectional Output Port 2—This output is generated by the MPC875 as a
result of a write to the PGCRB register in the PCMCIA interface.
Mode Clock 1—Input sampled when PORESET is negated to
configure PLL/clock mode.
Special Transfer Start—The MPC875 drives this output to indicate
the start of an external bus transfer or an internal transaction in
show-cycle mode.
OP3
MODCK2
DSDO Hi-Z B2 Bidirectional Output Port 3—This output is generated by the MPC875 as a
result of a write to the PGCRB register in the PCMCIA interface.
Mode Clock 2—This input is sampled at the PORESET negation
to configure the PLL/clock mode of operation.
Development Serial Data Output—Output data from the debug
port interface.
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Name
Hard
Reset
Number Type Description