AAL2 Implementation
MPC885 PowerQUICC Family Reference Manual, Rev. 2
44-4
Freescale Semiconductor
mechanism is enabled for this channel, the Timer CU count down for this AAL2 channel is also started. If
the Timer CU counter expires before the active buffer becomes full, AAL2 activates in order to pad the
buffer with zeros and mark its BD as ready. This buffer (along with other ready AAL0 buffers of the
channel) is then transmitted in a separate process by the MPC885 according to the APC scheduling or host
scheduling (using
APC
BYPASS
).
If AAL2 is activated to process a channel’s partially filled active buffer before its Timer CU counter
expired, the active buffer is filled with CPS-Packets, the active BD is closed (R bit is set) and the channel’s
Timer CU counter is deactivated. However, if the active buffer is still not full, the Timer CU counter
continues its count down.
44.2.2
AAL2 Receive Overview
The MPC885 receives AAL0 cells and places them in the external memory. Because all of the RxBDs
associated with AAL2 channels must have the I bit set, the same as for the TxBDs, the MPC885 attempts
to generate an interrupt to the host. However, as the IMASK[AAL2] bit is set, AAL2 processing is invoked
instead.
For each activation, the AAL2 receiver processes one active AAL0 buffer. AAL2 does the following:
•
Checks the STF field of the CPS-PDU
•
Breaks the CPS-PDU into CPS-Packets
•
Verifies the HEC for each CPS-PH
•
Copies each CPS-Packet to external memory according to the pointer in the current RPD of the
channel’s AAL2_Rx_Queue
•
Checks the CPS-PDU for errors. If an error is detected, an indication is written to the associated
RPD and the CPS-Packet is discarded. See
Section 44.5.1, “Receive Packet Descriptor (RPD),”
for
a description of the possible errors.
•
If a complete CPS-Packet is retrieved from the active buffer, the RPD will be marked as available
to the host (E = 0). If RPD[INT] is set and the interrupt is not masked by AAL2_RCT[RPI], the
AAL2 adds an entry to the exception queue (with the AAL2 bit and RXB bit set) to signal the host
that a CPS-Packet has been received. The global interrupt count (INT_CNT) is also decremented.
If INT_CNT reaches zero, the global interrupt (GINT) bit in the event register is set and an
interrupt is generated to the host. (The INT_CNT is then restored to the INT_ICNT value.) If the
exception queue is already full, the IQOV bit is set in the event register—entries in the exception
queue are not overwritten. The host may then service the exception queue and process the
appropriate AAL2_Rx_Queues and mark their RPDs as empty (E=1).
•
If only a partial CPS-Packet is retrieved from the AAL0 buffer, AAL2 stores the CPS-Packet
parameters in the channel’s AAL2_RCT. When the AAL2 is next activated to serve this channel
(after a new cell has been placed in an AAL0 buffer), it resumes operation from where it stopped.
•
If the complete AAL0 buffer is processed, its BD is marked empty. If, however, AAL2 could not
finish processing the AAL0 buffer (because there are not enough available RPDs in the
AAL2_Rx_Queue), the CPS-PDU will be discarded and an entry is added to the exception queue
(with the AAL2 bit and OVF bit set) to indicate an AAL2_Rx_Queue overflow.
Summary of Contents for PowerQUICC MPC870
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