Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Byte Ordering
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor A-7
MSR[ILE] is used to set the endian mode of the core during exception handling. When an exception
occurs, MSR[ILE] is copied into MSR[LE] to select the endian mode for the context established by the
exception.
For PPC-LE-mode, the FCR[BO] parameter of each peripheral (SCCs, SMCs, SPI, I
2
C, PIP, or IDMA)
should be set to 0b01. The SDMA controller examines the BO parameter and, if set to 0b01, performs a
3-bit munge (XOR with 0b111) on every byte address of transmitted or received data as in
Table A-6 .
A.5.1 I/O Addressing in PPC-LE Mode
For a system running in BE or TLE mode, both the MPC885 and the memory subsystem recognize the
same byte as byte 0. However, this is not true for a system running in PPC-LE mode because of the munged
address bits when the accesses external memory.
For I/O transfers in PPC-LE mode to transfer bytes properly, they must be performed as if the bytes
transferred were accessed one at a time, using the little-endian address modification appropriate for the
single-byte transfers (that is, the lowest order address bits must be XORed with 0b111). This does not mean
that I/O operations in PPC-LE systems must be performed using only one-byte-wide transfers. Data
transfers can be as wide as desired, but the order of the bytes within double words must be as if they were
fetched or stored one at a time. That is, for a true little-endian I/O device, the system must provide a
mechanism to munge and unmunge the addresses and reverse the bytes within a doubleword (MSB to
LSB).
A load or store that maps to a control register on an external device may require the bytes of the register
data to be reversed. If this reversal is required, the load and store with byte-reverse instructions (lhbrx,
lwbrx, sthbrx, and stwbrx) may be used.
A.6 Setting the Endian Mode Of Operation
As shown in Table A-1 , the MPC885 powers up in BE mode. The endian mode should be set early in the
initialization routine and remain unchanged for the duration of system operation. To switch between the
different endian modes of operation, the core must run in serialized mode and the caches should be
disabled. It is not recommended that you switch back and forth between modes.
To switch the system from BE to PPC-LE mode, the MSR[LE] and MSR[ILE] bits should be set using an
mtmsr instruction that resides on an odd word boundary (A[29] = 1). The instruction that is executed next
will be fetched from this address plus 8. If the mtmsr instruction resides on an even word boundary (A[29]
= 0), then the instruction will be executed twice due to the address munging of PPC-LE mode.
To switch the system from PPC-LE to BE mode, the MSR[LE] and MSR[ILE] bits should be cleared using
an mtmsr instruction that resides on an even word boundary (A[29] = 0). The instruction that is executed
next will be fetched from this address plus 12.
To switch the system to TLE mode, DC_CST[LES] should be set using an mtspr instruction that resides
on an even word boundary (A[29] = 0). Further instructions should reside in the little-endian format of the
external system memory or in the big-endian format of the internal memory (if it exists).
The buffer descriptors for the peripherals contain the FCR[BO] parameters for the SDMA controller. The
BO parameter should be set to the required endian format prior to activating the associated peripheral.