Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Memory Management Unit
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 8-27
8.8.12.4 DMMU CAM Entry Read Register (MD_CAM)
When the DMMU CAM entry read register (MD_CAM), shown in Figure 8-20 , is read, it contains the
effective address and page sizes of an entry indexed by MD_CTR[DTLB_INDX]. This register is updated
when a value is written to it.
Table 8-20 describes MD_CAM fields.
30 PV Page validity
0 Page is not valid
1 Page is valid
31 G Guarded memory attribute for entry
0 Nonguarded memory
1 Guarded memory
0 15
Field EPN
Reset —
R/W R(/W)
16 19 20 23 24 26 27 28 31
Field EPN SPVF PS SH ASID
Reset —
R/W R(/W)
SPR 824
Figure 8-20. DMMU CAM Entry Read Register (MD_CAM)
Table 8-20. MD_CAM Field Descriptions
Bits Name Description
0–19 EPN Effective page number
20 SPVF Subpage validity flags
0 Subpage 0 (address[20–21] = 00) is not valid
1 Subpage 0 (address[20–21] = 00) is valid
21 0 Subpage 1 (address[20–21] = 01) is not valid
1 Subpage 1 (address[20–21] = 01) is valid
22 0 Subpage 2 (address[20–21] = 10) is not valid
1 Subpage 2 (address[20–21] = 10) is valid
23 0 Subpage 3 (address[20–21] = 11) is not valid
1 Subpage 3 (address[20–21] = 11) is valid
Table 8-19. MI_RAM1 Field Descriptions (continued)
Bits Name Description