Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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The MPC8xx Core
MPC885 PowerQUICC Family Reference Manual, Rev. 2
3-14 Freescale Semiconductor
3.7 The MPC885 and Implementation of the PowerPC Architecture
This section describes the relationship between the MPC885 and implementation of the PowerPC
architecture. It indicates the types of distinguishing features of the MPC885 described in the following:
• In many cases, the PowerPC architecture specification is flexible enough to allow implementation
options. For example, the architecture does not specify whether unaligned transfers must be
handled in hardware or whether instruction execution must be performed in hardware or software.
• The PowerPC architecture defines optional features, some of which are implemented on the
MPC885 (such as TLBs) and some of which are not, such as the eciwx and ecowx instructions.
• The PowerPC architecture defines features, such as virtual memory and floating-point instructions,
that are not implemented on the MPC885.
Table 3-3 summarizes MPC885 features with respect to the UISA definition.
Table 3-3. UISA-Level Features
Functionality Description
Reserved fields Reserved fields in instructions are described under the specific instruction definition in Chapter 5,
“MPC885 Instruction Set.” Unless otherwise stated, instruction fields marked I, II, and III are
discarded during decoding. Thus, this type of instruction yields results of the defined instructions
with the appropriate field = 0. In most cases, reserved fields in registers are ignored on write and
return zeros for them on read for any control register implemented by the core. Exceptions are
XER[16–23] and the reserved bits of MSR, which are set by the source value on write and return
the value last set for it on read.
Classes of
instructions Required instructions (except floating-point load, store, and compute instructions) are
implemented in hardware. Optional instructions are executed by implementation-dependent code;
any attempt to execute one of these commands causes the core to take the software emulation
exception (offset 0x01000). Illegal and reserved instruction class instructions are supported by
implementation-dependent code and, thus the core hardware generates a software emulation
exception.
Exceptions Invocation of the system software for any exception caused by an instruction in the core is precise,
regardless of the type and setting.
Fetching
instructions The core fetches a number of instructions into its IQ from which they are dispatched to the
execution units. If a program modifies instructions, it should call a system library program to ensure
that the instruction fetching mechanism can detect changes before execution.
Branch
instructions The core implements all UISA instructions defined for the branch processor in hardware. For
details about the performance of various instructions, see Table 3-1.
Invalid branch
instruction forms Bits marked with z in the BO encoding definition default to z = 0 and are discarded by the core
decoding. Thus, these instructions yield results of defined instructions for which z = 0. If the
decrement and test CTR option is specified for the
bcctr or bcctrl instructions, the target address
of the branch is the new value of the CTR. Condition is evaluated correctly, including the value of
the counter after decrement.
Branch prediction The core uses the y bit to predict path for prefetch. Prediction is only done for not-ready branch
conditions. No prediction is done for branches to the link or count register if the target address is
not ready (see
Table 3-1 ).