ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–7
5.2.3 Interrupt Enable Register 23 (IE23)
Address: 0F012H
Access: R/W
Access size: 8/16 bits
Initial value: 0000H
7
6
5
4
3
2
1
0
IE2
–
EUAF0
EUA1
EUA0
EI2C1
EI2C0
ESIOF0
ESIO0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
IE3
EMD0
EVLS
ELOSC
–
–
–
–
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
IE23 is a special function register (SFR) used to control enable/disable for each interrupt request.
When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of
IE23 is not reset.
Description of Bits
•
ESIO0
(bit 0)
ESIO0 is the enable flag for the synchronous serial port 0 interrupt (SIO0INT).
ESIO0
Description
0
Disabled (initial value)
1
Enabled
•
ESIOF0
(bit 1)
ESIOF0 is the enable flag for the synchronous serial port 0 interrupt with FIFO (SIOF0INT).
ESIOF0
Description
0
Disabled (initial value)
1
Enabled
•
EI2C0
(bit 2)
EI2C0 is the enable flag for the I2C bus 0 interrupt (I2C0INT).
EI2C0
Description
0
Disabled (initial value)
1
Enabled
•
EI2C1
(bit 3)
EI2C1 is the enable flag for the I2C bus 1 interrupt (I2C1INT).
EI2C1
Description
0
Disabled (initial value)
1
Enabled
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...