Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 9 Function Timer(FTM)
FEUL620Q504 9–12
9.2.7 FTMn Control Register 0 (FTnCON0 : n=0,1,2,3)
Address: 0F40AH(FT0CON0), 0F42AH(FT1CON0), 0F44AH(FT2CON0), 0F46AH(FT3CON0)
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
FTnCON0 – – FTnSDN – FTnEMGEN – FTnTGEN FTnRUN
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
FTnCON0 is a special function register (SFR) used to set the function of FTMn.
Description of Bits
•
FTnRUN (bit 0)
Stop/start counting of FTMn by the software.
FTnMD FTnRUN Description
TIMER
CAPTURE
PWM1/2
0 Stop counting (initial value)
1 Start counting/during counting
•
FTnTGEN (bit 1)
Allow stopping/starting counting by a trigger event.
FTnMD FTnGTEN Description
TIMER
CAPTURE
PWM1/2
0 Trigger operation disabled (initial value)
1 Trigger operation enabled
•
FTnEMGEN (bit 3)
Allow emergency stop of FTMn.
FTnMD FTnEMGEN Description
TIMER
PWM1/2
0 Emergency stop disabled (initial value)
1 Emergency stop enabled
CAPTURE * This bit is disabled.
•
FTnSDN (bit 5)
Mask the output of FTMn to L.
FTnMD FTnSDN Description
TIMER
PWM1/2
0 Release the output mask (initial value)
1 Set the output mask (fix output to L).
CAPTURE * This bit is disabled.