Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–36
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L1-0TM3 (bits 7 to 6)
L1-0TM3 set the level of the 8-bit timer 3 interrupt (TM3INT).
L1TM3 L0TM3 Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4
•
L1-0TM4 (bits 9 to 8)
L1-0TM4 set the level of the 8-bit timer 4 interrupt (TM4INT).
L1TM4 L0TM4 Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4
•
L1-0TM5 (bits 11 to 10)
L1-0TM5 set the level of the 8-bit timer 5 interrupt (TM5INT).
L1TM5 L0TM5 Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4
•
L1-0TM6 (bits 13 to 12)
L1-0TM6 set the level of the 8-bit timer 6 interrupt (TM6INT).
L1TM6 L0TM6 Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4
•
L1-0TM7 (bits 15 to 14)
L1-0TM7 set the level of the 8-bit timer 7 interrupt (TM7INT).
L1TM7 L0TM7 Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4
[Note]
A write instruction to the interrupt level control register 5 (ILC5) should be executed after disabling the
interrupt.
Except this way, the write instruction to the interrupt level control register 5(ILC5) is not guaranteed.