Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User’s Manual
Chapter 8 Timers
FEUL620Q504 8–12
8.3.2 One shot timer mode operation
When TMnCON register TnOST bit set to “1”, Timer operate one-shot timer mode.
In one-shot timer mode, When the count value (TMnC) and the timer 0 to 7 data register (TMnD) coincide,
TnRUN bits are cleared automatically .
Figure 8-3 shows the one-shot timer mode operation timing diagram
Figure 8-3 One-Shot Timer Mode Operation Timing Diagram
8.3.3 16bit timer mode
Two of 8bit timer can be used as 16bit timer by TMnCON(N=0,2,4,6) register TnM16 bit.
At 16bit timer mode, channel n(n=0.2.4.6) is lower bit, channel m(m=1,3,5,7) is higher bit.
The following shows a corresponding list of timer-channels and related registers.
channel
Control
0,1 2,3 4,5 6,7
Data rgister
Higher
：
TM1D
Lower
：
TM0D
Higher
：
TM3D
Lower
：
TM2D
Higher
：
TM5D
Lower
：
TM4D
Higher
：
TM7D
Lower
：
TM6D
Counter regiser
Higher
：
TM1C
Lower
：
TM0C
Higher
：
TM3C
Lower
：
TM2C
Higher
：
TM5C
Lower
：
TM4C
Higher
：
TM7C
Lower
：
TM6C
Controll register TM0CON TM2CON TM4CON TM6CON
RUN bit T0RUN T2RUN T4RUN T6RUN
STOP bit T0STP T2STP T4STP T6STP
STATbit T0STAT T2STAT T4STAT T6STAT
Interrupt TM1INT TM3INT TM5INT TM7INT
TMnC
XX 00
88
TMnD
TMnINT
TnSTAT
Write TMnC
TnCK
01 02
87 88 00
88 88
(n=0 to 7)
T
TMI
01
T
TMI
TnRUN
TnSTP