ML620Q503/Q504 User's Manual
Chapter 27
Flash Memory Control
FEUL620Q504 27-
13
27.3.5 Boot Area Remap Function by Hardware
When the power-on reset by power-on or the reset by the RESET_N pin is released under the condition that the
external pin (TEST0) is set to High, 512 bytes of ISP boot area
*
and 512 bytes of test area (1 KB in total) are
remapped to 0:0000H to 0:03FFH to allow the boot by the program in the ISP boot area. The ISP boot area is
also remapped to 0:0400H to 0:0FFF repeatedly.
By writing the boot program in the ISP boot area in advance, the following functions can be achieved:
When startup cannot be performed due to power down while rewriting the block 0 (area of 16 KB from
0000H) of FLASH, where the boot program is normally placed, startup (boot) from the ISP boot area can
avoid a situation that recovery is not possible.
The boot program can rewrite the internal program of the LSI by using UART which provides external
communication. This can achieve a function equivalent to Flash Writer.
*: The ISP boot area differs among products. (0:FC00H to 0:FDFFH for ML620Q504).
Figure 27-4 shows the memory map before and after remapping.
Figure 27-4 Boot Switch by Setting External Pin (TEST0)
0:0000H
Normal boot area
Test area
(Read-only)
0:FC00H
0:FE00H
0:0000H
Program area
Program area
Normal boot (TEST0 pin = L) before remapping
ISP boot (TEST0 pin = H) after remapping
Remapping
0:1000H
Test area
(Writable)
Test area
(Read-only)
0:FC00H
0:FE00H
ISP boot area
Test area
(Read-only)
ISP boot area
Test area
(Read-only)
ISP boot area
Test area
(Read-only)
ISP boot area
Test area
(Read-only)
ISP boot area
0:1000H
0:0400H
0:0800H
0:0C00H
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...