ML620Q503/Q504 User's Manual
Chapter 6 Clock Generation Circuit
FEUL620Q504
6–7
•
OSCM1-0
(bits 4 to 3)
The OSCM1-0 bits are used to select the high-speed clock mode. Crystal/ceramic oscillation mode,
built-in RC oscillation mode, or external clock input mode can be selected.
OSCM1 and OSCM0 can be rewritten only when high-speed oscillation is being stopped (ENOSC bit
of FCON1 is "0").
At system reset, the built-in RC oscillation mode is selected.
When switching the high-speed clock mode, please first stop high-speed oscillation(set the ENOSC bit
of FCON1 register to “0”) and then switch the system clock back to the low-speed clock (set SYSCLK
bits of the FCON1 register to "0").
OSCM1
OSCM0
Description
0
0
Setting prohibited (the setting is ignored and the previous value is
held)
0
1
High-speed Crystal/ceramic oscillation mode
1
0
High-speed Built-in RC oscillation mode (initial value)
1
1
External high-speed clock input mode
•
OUTC2-0
(bits 7 to 5)
The OUTC2, OUTC1, and OUTC0 bits select the frequency of the high-speed output clock (OUTCLK)
output when the secondary function of the port is used. 1/1OSCLK, 1/2OSCLK, 1/4OSCLK, 1/8OSCLK,
1/16OSCLK, or 1/32OSCLK can be selected.
At system reset, 1/8OSCLK is selected.
OUTC2
OUTC1
OUTC0
Description
0
0
0
1/1OSCLK
0
0
1
1/2OSCLK
0
1
0
1/4OSCLK
0
1
1
1/8OSCLK (initial value)
1
0
0
1/16OSCLK
1
0
1
1/32OSCLK
1
1
0
Setting prohibited (1/32OSCLK)
1
1
1
Setting prohibited (1/32OSCLK)
•
SYSCLK
(bit 8)
The SYSCLK bit is used to select system clock. The low-speed clock (LSCLK) or the HSCLK
(1/nOSCLK: n = 1,2, 4, 8, 16, 32) selected by the FCON0 high-speed clock frequency selection bit
(SYSC2,1,0) can be selected.
When the oscillation of high-speed clock is stopped (ENOSC bit = "0"), the SYSCLK bit is fixed to "0"
and the low-speed clock (LSCLK) is selected for system clock.
SYSCLK
Description
0
LSCLK
1
HSCLK (initial value)
•
ENOSC
(bit 9)
The ENOSC bit is used to select enable/disable of the oscillation of the high-speed clock oscillator
circuit.
ENOSC
Description
0
Disables high-speed oscillation
1
Enables high-speed oscillation (initial value)
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...