Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 4 Power Management
FEUL620Q504 4-14
4.3.2 STOP Mode
During the STOP mode, the low-speed oscillation and high-speed oscillation stop and the CPU and peripheral
circuits stop the operation.
When the stop code acceptor is enabled by successively writing “5nH” and “0AnH” (where n is 0 to 0FH) to the
stop code acceptor (STPACP) and the STP bit of the standby control register (SBYCON) is set to “1”, the STOP
mode is entered. When the STOP mode is set, the STOP code acceptor is disabled.
When an external pin interrupt request that is interrupt-enabled (the interrupt enable flag is “1”) is issued, the
STP bit is set to “0”, the STOP mode is released, and the mode is returned to the program run mode.
[Note]
•When the mode switch to STOP mode at High speed oscillator is used,
Frequency Status Register (FSTAT) HOSCS bit must be “0”.
•After release of the STOP mode, interrupts other than WDT interrupt start being processed if they are
enabled (“1”) by the MIE bit of PSW.
For details of PSW, refer to “nX-U16/100 Core Instruction Manual”
•Since up to two instructions are executed during the period between STOP mode release and a transition to
interrupt processing, place two NOP instructions next to the instruction that sets the STP bit to “1”.
4.3.2.1 Oscillation Stop and Restart Timing of Low-Speed Clock
When the stop code acceptor is in the enabled state and the STP bit of SBYCON is set to “1”, the STOP mode is
entered, stopping low-speed oscillation and high-speed oscillation.
When an external pin interrupt request that is interrupt-enabled (the interrupt enable flag is “1”) is issued, the
STP bit is set to “0”, and the low-speed oscillation restarts. If the high-speed clock was oscillating before the
STOP mode is entered, the high-speed oscillation restarts. When the high-speed clock was not oscillating before
entering the Stopped state, high-speed oscillation does not start.
After generating interrupt request, low-speed built-in RC oscillation begins oscillating independently of the clock
mode. And, the clock is supplied as LSCLK after counts 29. When a system clock is a low-speed clock, it returns
to program operational mode simultaneously.
In the case of low-speed crystal oscillation mode, oscillation is started after low-speed oscillation start time
(T
XTL
) by interrupt request occurs. And, LSCLK changes from RC oscillation into crystal oscillation by the
automatic operation in after counts 8192 by the crystal oscillation.
In the case of high-speed external clock mode, LSCLK changes from RC oscillation into external clock by the
automatic operation after counts 16 by the external clock by interrupt request occurs.
For the low-speed oscillation start time (T
XTL
), see Appendix C “Electrical Characteristics”.
Figure 4-5 shows the operation waveforms in STOP mode when CPU operates with the low-speed clock.