Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-9
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UF0BC (bit 6)
UF0BC selects the break control of UARTF0.
Turning this to "1" brings the UARTF0 data output (TXDF0) to the spacing state (logical 0). The control
by this bit is valid only on the TXDF0 pin. This means that TXDF0 is masked but the transmit operation
continues internally. The use of the break control allows the CPU to send an alarm to the terminal of the
computer communication system.
UF0BC Description
0 Break control not implemented (initial value)
1 Break control implemented
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UF0DLAB (bit 7)
UF0DLAB selects the access register of UAF0BUF.
When this is "0", RBR and THR are accessible. When this is "1", DLR is accessible.
UF0DLAB Description
0 RBR and THR of UAF0BUF are accessible (initial value)
1 DLR of UAF0BUF is accessible
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UF0FEN (bit 8)
UF0FEN selects whether FIFO is enabled or disabled for UARTF0.
UF0FEN Description
0 FIFO disabled (initial value)
1 FIFO enabled
[Note]
FIFO will be cleared when switching between FIFO enable/disable.
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UF0RFR (bit 9)
UF0RFR instructs to reset the receive FIFO of UARTF0.
UF0RFR Description
0 Receive FIFO normal operation (initial value)
1 Clears the receive FIFO
[Note]
When the receive clearance is selected, data being received is not cleared.
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UF0TFR (bit 10)
UF0TFR selects to clear the transmit FIFO of UARTF0.
UF0TFR Description
0 Transmit FIFO normal operation (initial value)
1 Clears the transmit FIFO
[Note]
When the transmit clearance is selected, data being transmitted is not cleared.