ML620Q503/Q504 User’s Manual
Chapter 26 Analog Comparator
FEUL620Q504 26–3
26.2.2 Comparator n Control Register (CMPnCON : n=0,1)
Address: 0F920H(CMP0CON), 0F928H(CMP1CON)
Access: R/W
Access size: 8 bits
Initial value: 00H
7
6
5
4
3
2
1
0
CMPnCON
–
–
–
–
–
CMPnRF
CMPnD
CMPnEN
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
Initial value
0
0
0
0
0
0
0
0
CMPnCON is a special function register (SFR) to control the Comparator.
Description of Bits
•
CMPnEN
(bit 0)
The CMPnEN bit is used to control activation (ON) or deactivation (OFF) of the Comparator n.
It is used to indicate Comparator active status.
CMPnEN
Description
0
Deactivates the Comparator n measurement is stopped(initial value)
1
Activates the Comparator n measurement is in progress
•
CMPnD
(bit 1)
The CMPnD bit indicates the status of comparator n output (CMPnOUT shown in the Figure 26-1).
It is set to “1” when the voltage at CMPnP pin is larger than the voltage at CMPnM pin (CMPnP > CMPnM), is set
to “0” when the voltage at CMPnP pin is smaller than the voltage at CMnPM pin (CMPnP < CMPnM).
The last status of this bit remains after the comparator is deactivated(“0” is set to CMPnEN).
CMPnD
Description
0
CMPnP < CMPnM (initial value)
1
CMPnP > CMPnM
•
CMPnRF
(bit 2)
The CMPnRF indicate the status of comparator n measurement setting.
CMPnD is invalid until CMPnRF bit becomes 1 after starting measurement.
CMPnRF
Description
0
CMPnD is invalid (initial value)
1
CMPnD is valid
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...