ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-1
14 UART with FIFO (UARTF)
14.1 General Description
The UART with FIFO (UARTF) functions as the input/output interface, carries out serial-to-parallel conversion
of the data sent from the peripheral devices, and also converts the parallel data sent from the CPU into serial data.
The UARTF has a 4-byte FIFO for transmission and reception, capable of storing up to 4 bytes of data during
transmission/reception in the FIFO mode.
Further, the receive FIFO generates 3 bits of error data for every byte of received data. The CPU can read out the
UARTF state at any time. The information that can be read out consists of the type and status of the transfer
operation under execution, and the statuses of errors such as parity, overrun, framing errors, and break interrupt,
etc.
The I/O pins of the UARTF are assigned as the tertiary function of the ports 2, 3, 4, and 5. For the ports 2, 3, 4,
and 5, see Chapter 19 "Port 2", Chapter 20 "Port 3", Chapter 21 "Port 4", and Chapter 22 "Port 5".
14.1.1 Features
•
Full duplex buffer system
•
All status reporting function
•
4-byte transmit and receive FIFOs
•
Independent control of transmit, receive, line status data set interrupt and FIFO
•
Programmable serial interface
–
5-, 6-, 7-, and 8-bit characters
–
Odd parity, even parity, no parity generation and verification
–
1, 1.5, or 2 stop bits
•
Communication speed: Settable within the range of 2400bps to 115200bps.
•
Built-in baud rate generator.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...