ML620Q503/Q504 User's Manual
Chapter 6 Clock Generation Circuit
FEUL620Q504
6–25
6.3.3 Switching of System Clock
The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using
the frequency control registers (FCON0, FCON1).
Figure 6-15 shows the flow chart of the system clock switching processing (HSCLK
→
LSCLK), and Figure 6-16
shows the flow chart of the system clock switching processing (LSCLK
→
HSCLK).
Figure 6-15 Flow Chart of System Clock Switching Processing (HSCLK
→
LSCLK)
[Note]
If the system clock is switched from the high-speed clock to the low-speed clock before the low-speed clock
(LSCLK) starts oscillation, the CPU becomes the stopped state until LSCLK starts to be supplied to the
peripheral circuits.
Figure 6-16 Flow Chart of System Clock Switching Processing (LSCLK
→
HSCLK)
System clock switching
ENOSC
←
"1"
Wait of the oscillation
stabilization time
(T
WAIT
)
SYSCLK
←
"1"
High-speed
operation mode
T
WAIT
is 50us in low-speed built-in RC oscillation mode, or 1ms in other
low-speed oscillation mode.
If waiting high-speed crystal/ceramic oscillation, it is recommended
seeing the HOSCS bit of FSTAT becomes “0”.
Before switching the system clock, set the high-speed oscillation
mode.
High-speed oscillation start
Switches the system clock (low-speed clock to high-speed clock)
System clock switching
SYSCLK
←
"0"
Low-speed
operation mode
Switches the system clock (high-speed clock to low-speed clock)
ENOSC
←
"0"
Stops high-speed oscillation
(* Not needed to stop in the case when the high-speed clock
is used by something other than the CPU)
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...