Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User’s Manual
Contents
FEUL620Q504 contents–3
5.3 Description of Operation
........................................................................................................... 5-51
5.3.1 Interrupt Source ........................................................................................................ 5-51
5.3.2 Maskable Interrupt Processing ................................................................................. 5-53
5.3.3 Non-Maskable Interrupt Processing ......................................................................... 5-53
5.3.4 Software Interrupt Processing .................................................................................. 5-53
5.3.5 Notes on Interrupt Routine........................................................................................ 5-54
5.3.6 Interrupt Processing When Interrupt Level Control Enabled .................................... 5-58
5.3.7 Flow Chart (When Interrupt Level Control Enabled) ................................................ 5-59
5.3.8 Interrupt Disable State .............................................................................................. 5-61
5.3.9 External Interrupt ...................................................................................................... 5-62
Chapter 6
6. Clock Generation Circuit ................................................................................................................... 6-1
6.1 General Description
.................................................................................................................... 6-1
6.1.1 Features ...................................................................................................................... 6-1
6.1.2 Configuration ............................................................................................................... 6-1
6.1.3 List of Pins .................................................................................................................. 6-3
6.1.4 Clock Configuration Diagram ...................................................................................... 6-4
6.2 Description of Registers ............................................................................................................. 6-5
6.2.1 List of Registers .......................................................................................................... 6-5
6.2.2 Frequency Control Register 01 (FCON01) ................................................................. 6-6
6.2.3 Frequency Control Register 23 (FCON23) ................................................................. 6-9
6.2.4 Frequency Status Register (FSTAT) ........................................................................ 6-11
6.3 Description of Operation
........................................................................................................... 6-12
6.3.1 Low-Speed Clock ...................................................................................................... 6-12
6.3.1.1 Low-Speed Built-in RC Oscillation Mode ........................................................... 6-12
6.3.1.2 Low-Speed Crystal Oscillation Mode .................................................................. 6-12
6.3.1.3 Low-Speed External Clock Input Mode
.............................................................. 6-13
6.3.1.4 Low-Speed Built-In RC Oscillation Mode Operation
......................................... 6-14
6.3.1.5 Low-Speed Crystal Oscillation Mode Operation
................................................ 6-15
6.3.1.6 Low-Speed External Clock Mode Operation
...................................................... 6-16
6.3.2 High-Speed Clock ..................................................................................................... 6-17
6.3.2.1 High-Speed Built-in RC Oscillation Mode
.......................................................... 6-17
6.3.2.2 High-Speed Crystal/Ceramic Oscillation Mode .................................................. 6-17
6.3.2.3 High-Speed External Clock Input Mode ............................................................. 6-18
6.3.2.4 High-Speed Built-In RC Oscillation Mode Operation ........................................ 6-19
6.3.2.5 High-Speed Crystal/Ceramic Oscillation Mode Operation ................................ 6-20
6.3.2.6 High-Speed External Clock Mode Operation
..................................................... 6-23
6.3.3 Switching of System Clock ....................................................................................... 6-25
6.3.4 Low-speed oscillation clock switch interrupt ............................................................. 6-26
Chapter 7
7. Time Base Counter ........................................................................................................................... 7-1
7.1 Overview ...................................................................................................................................... 7-1
7.1.1 Features ...................................................................................................................... 7-1
7.1.2 Configuration ............................................................................................................... 7-1
7.2 Description of Registers
............................................................................................................. 7-2
7.2.1 List of Registers .......................................................................................................... 7-2
7.2.2 Low-Speed Time Base Counter (LTBR) ..................................................................... 7-3
7.2.3 Low-Speed Time Base Counter Frequency Adjustment Registers (LTBADJ)........... 7-4
7.2.4 Low-Speed Time Base Counter Interrupt select Registers (LTBINT) ........................ 7-6
7.3 Description of Operation ............................................................................................................. 7-7
7.3.1 Low-Speed Time Base Counter ................................................................................. 7-7