Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 12 Synchronous Serial Port with FIFO
FEUL620Q504 12–25
12.3.9 Receive Operation (Master Mode)
The master mode of the synchronous serial with FIFO starts by setting data in a transmission buffer.
Data needs to be set into a transmission buffer even master mode reception only.

Write the necessary values to SF0CTRL, SF0INTC, SF0BRR, and SF0TRAC, set the SF0MST bit to
Master mode, and set the SF0SPE bit to enable the SSIOF transfer.

When the data is written to SF0DWR, the SSIOF transfer is started.

The sync clock, which was set by the SF0CPOL, SF0CPHA, and SF0BRR0-1 registers, is output from the
SCKF0 pin.

On the SINF0 pin, the received data is sampled from LSB or MSB according to the SF0LSB setting and
stored in the receive FIFO. The receive FIFO Empty flag changes to 0 (RFE = 0).

The SF0SPIF bit is set each time the transfer of 1 byte is completed. (SF0SPIF=1)

If the number of data received in the receive FIFO is equal to or more than matches following the byte count
selected with SF0RFIC of SF0CR, SF0RFI of SF0SRR is set to generate a reception interrupt.

When the receive FIFO becomes Full, the subsequent reception is disabled. If the reception is performed in
this state, an overrun error interrupt is generated. (SF0ORF=1)

If the temporary data of transmit FIFO becomes empty and the transfer of the last byte is completed, a
transfer completion interrupt is generated. (SF0FI=1)
Figure 12-9 Master Mode (Receive Operation)
SSF0
SCKF0
SINF0
SF0SPE
write from
U16IF
read from
U16IF
SF0RFE
SF0RFF
SF0ORF
SF0TFD
SF0RFIC
SSIOF
interrupt
signal
0 2
0 1 1 2
SF0CTRL
data1
data5
3 0 3 4
SF0SRC
status
RFI
reception
interrupt
Receive data 1 Transfer data 5 2 4
SF0RFD
0
2 1
1
2 3 4
SF0SRC
status
data1
data4
3 2 1 0
3
ORF
overrun error
interrupt