Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 2 CPU and Memory Space
FEUL620Q504 2–1
2. CPU and Memory Space
2.1 General Description
The CPU nX-U16/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage
pipeline architecture parallel processing. It can also perform multiplication/division and multiply-accumulate
operation by a coprocessor.
2.1.1 Features
• 16-bit RISC CPU (CPU name: nX-U16/100)
• Instruction system: 16-bit length instruction
• Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
• Built in On-chip debug function
• Minimum instruction execution time
30.5
μs (@32.768kHz system clock)
62.5ns (@16MHz system clock)
• Multiplication/division coprocessor mounted
2.1.2 Notes When Executing SB/RB Instruction
The bit manipulation SB/RB instruction reads in bytes from a register containing the target bits, generates the
byte data while rewriting only the values of the target bits, then writes it in bytes.
If an SB/RB instruction is executed to a register where multiple bits are placed, bits not targeted for the SB/RB
instruction are rewritten with the values read at that time.
Note that the SB/RB instruction may rewrite the state of bits not targeted for the SB/RB instruction if it is
executed to a register where values of some bits change depending on the hardware state.