Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User’s Manual
Chapter 10 Watchdog Timer
FEUL620Q504 10–3
10.2.2 Watchdog Timer Control Register (WDTCON)
Address: 0F00EH
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
WDTCON d7 d6 d5 d4 d3 d2 d1 WDP/d0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
WDTCON is a special function register (SFR) to control the Watchdog Timer.
When write to WDTCON, the value of the internal pointer (WDP) is reversed .
WDT counter is cleared when “5AH” and “0A5H” is written to WDTCON in succession.
The value in WDP is read from bit0 when WDTCON is read. In this time “0” is read from bit7-bit1.
WDP is reset to “0” at system reset and at overflow.
For WDT counter clear, write “5AH” when WDP state is “0” and write “0A5H” when WDP state is “1”.
If WDT state is different from above, WDT counter cannot be cleared, even if these clear data is written.
This register requires byte access always.
[Note]
When the WDT interrupt(WDTINT) is occurred by the WDT counter first overflow, the WDT counter and the
internal pointer(WDP) are initialized for 1/2 clock period of low-speed clock(approximately
15.26us@32.768kHz). Therefore the writing to the WDTCON becomes invalid during the period and WDP is
not reversed. I In processing clear WDT when WDT interrupt occur and system clock is in high-speed clock
state, Confirm that WDP is reversed by writing to WDTCON and confirm the writing to WDTCON is done
normally.
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