Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–51
5.3 Description of Operation
5.3.1 Interrupt Source
With the exception of the watchdog timer interrupt (WDTINT), interrupt enable/disable for 37 sources is
controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE0 to 7).
WDTINT is a non-maskable interrupt.
When the interrupt conditions are satisfied, the program calls a branching destination address from the vector
table determined for each interrupt source and the interrupt shift cycle starts to branch to the interrupt processing
routine.
Table 5-1 lists the interrupt sources.
Table 5-1 Interrupt Sources
Interrupt
priority
level
Interrupt source Symbol Vector table address
1 Watchdog timer interrupt WDTINT 0008H
5 EXI0 interrupt EXI0INT 0010H
6 EXI1 interrupt EXI1INT 0012H
7 EXI2 interrupt EXI2INT 0014H
8 EXI3 interrupt EXI3INT 0016H
9 EXI4 interrupt EXI4INT 0018H
10 EXI5 interrupt EXI5INT 001AH
11 EXI6 interrupt EXI6INT 001CH
12 EXI7 interrupt EXI7INT 001EH
13 Synchronous serial port 0 interrupt SIO0INT 0020H
14
Synchronous serial port 0 interrupt with
FIFO
SIOF0INT 0022H
15 I2C bus 0 interrupt I2C0INT 0024H
16 I2C bus 1 interrupt I2C1INT 0026H
17 UART0 reception interrupt UA0INT 0028H
18 UART0 transmission interrupt UA1INT 002AH
19 UART0 interrupt with FIFO UAF0INT 002CH
26
low-speed oscillation clock switching
interrupt
LOSCINT 003AH
27 VLS interrupt VLSINT 003CH
28 Melody 0 interrupt MD0INT 003EH
29
Successive approximation type A/D
converter interrupt
SADINT 0040H
30 RC oscillation type A/D converter interrupt RADINT 0042H
33 Comparator 0 interrupt CMP0INT 0048H
34 Comparator 1 interrupt CMP1INT 004AH
37 Timer 0 interrupt TM0INT 0050H
38 Timer 1 interrupt TM1INT 0052H
39 Timer 2 interrupt TM2INT 0054H
40 Timer 3 interrupt TM3INT 0056H
41 Timer 4 interrupt TM4INT 0058H
42 Timer 5 interrupt TM5INT 005AH
43 Timer 6 interrupt TM6INT 005CH