ML620Q503/Q504 User's Manual
Chapter 23 Melody Driver
FEUL620Q504 23-7
23.3 Description of Operation
23.3.1 Operation of Melody Output
Melody is output in the following procedure.
(1)
Select melody mode by setting the BZMD bit of the melody 0 control register (MD0CON) to “0”.
(2)
Set a melody tempo in the melody 0 tempo code register (MD0TMP).
(3)
Set a tone length code in the melody 0 tone length code register (MD0LEN).
(4)
Set a scale code in the melody 0 scale code register (MD0TON).
(5)
When the M0RUN bit of the melody 0 control register (MD0CON) is set to “1”, the tone length code and
scale code are transferred to the tone length buffer and scale buffer and melody output is started from the
MD0 pin. At the same time, a melody 0 interrupt (MD0INT) is requested. When an interrupt occurs and
program is passed to the interrupt routine, the interrupt request flag is cleared.
The melody 0 signal output pin (MD0) is assigned as the secondary function of Port 3 or Port 4 or Port 5. For the
secondary function of Port 3 or Port 4 or Port 5, see Chapter 20, "Port 3" or Chapter 21, "Port 4", Chapter 22,
"Port 5".
In the software processing after melody 0 interrupt, the tone length code and the scale code of the note that are
output next are set to MD0LEN and MD0TON, respectively. When there is no next note to be output, rest data
“00H” is set in MD0TON, the M0RUN bit is set to “0” by the software processing after the next melody 0
interrupt, and melody output is terminated.
By setting the M0RUN bit to “0”, melody can be terminated forcibly during melody output.
Figure 23-2 shows the operation waveform of the melody driver.
Figure 23-2 Operation Waveform of Melody Driver
M0RUN
MD0INT
XX
1
st
sound
2
nd
sound
XX
1
st
sound waveform
2
nd
sound
3
rd
sound
3
rd
sound
Final sound
Rest data
Final sound
Rest data
MD0LEN
MD0TON
Tone length/Scale buffer
Melody output waveform
MD0*
2
nd
sound
waveform
3
rd
sound
waveform
1
st
sound
Final sound waveform
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...