ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-16
14.3 Description of Operation
The UART is programmed with UAF0IER, UAF0MOD, DLR(UAF0BUF), and UAF0CAJ. These registers
define the character length, number of stop bits, parity, baud rate, etc.
Though the registers can be written in any order, UAF0IER needs to be written to last because it controls the
interrupt enable. Once the UART is programmed to be operable, these registers can be updated any time when
the UART is not transmitting or receiving data.
14.3.1 Data Transmission
Figure 14-2 shows the transmission timing.
Writing data to THR will transfer the contents through the transmit FIFO to the transmit shift register. Within 16
baud rate clocks after the THRE bit rise is detected, the start bit is sent, followed by the data one bit at a time
from the least significant bit. When the data to be transmitted is 7-bit, the most significant bit will not be sent.
If parity is enabled by UF0PT2-0 of UAF0MOD, then the parity bit is sent. This is followed by the stop bit which
indicates the end of transmitting one frame of data.
After the data is transmitted, the UF0THRE bit of UAF0LSR is set to "1" to indicate that it is ready for the next
transmission. This bit is cleared when one byte is written to the transmit FIFO. Also, if the THRE interrupt is
enabled by UF0ETBEI of UAF0IER, THRE initiates a LVL=3 interrupt to UAF0IIR. If THRE is the interrupt
source indicated in UAF0IR, this bit is cleared by reading the UAF0IIR register.
TXDF0
Start
Data bit (5
~
8)
Parity
Stop
Start
(1or2)
tIRS
tSTI
UAF0INT
(THRE)
tSI
WR(THR)
RD
IIR Read
tIRS:
<16 Baud rate Clocks
tSI:
8
~
16 Baud rate Clocks
tSTI:
8 Baud rate Clocks
Figure 14-2 Transmission Timing
[Note]
Transmit FIFO is an empty state, but there is the case that all transmit processing doesn’t complete.
Confirm that transmit shift register (TSR) became empty in UF0TEMT bit of UAF0LSR register before
stopping high-speed clock (Transition to modes such as STOP / DEEP-HALT / HALT-H).
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...