Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 12 Synchronous Serial Port with FIFO
FEUL620Q504 12–20
12.3.4 Data Transfer Timing When SF0CPHA Is "1"
Figure 12-3 shows the data transfer timing when SF0CPHA is "1". For the SCKF0, two cases are shown
(SF0CPOL is "0" and "1").
SSF0 is the slave selection input in Slave mode.
In Master mode, the transfer is started when data is written to SF0DWR. In Slave mode, the transfer is started at
the first edge of SCKF0. The received data is sampled at the falling-edge of SCKF0 in SF0CPOL is “0” and the
rising-edge of SCKF0 in SF0CPOL is “1”. The transmitted data is shifted at the rising-edge of SCKF0 in
SF0CPOL is “0” and the falling-edge of SCKF0 in SF0CPOL is “1”.
CPHA=1
SSN
MOSI
(MOZ=0)
BIT 0 BIT 7
BIT 7 BIT 0
SCK Cycle
1 2 3 4 5 6 7 8
MISO
(SOZ=0)
SCK
(CPOL=0
)
SCK
(CPOL=1
)
MOZ=SOZ=SSZ=SIZE=LSBF=LEAD=LAG=0
の例
です。
Figure 12-3 Clock Waveform When CPHA = 1
12.3.5 Serial Clock Baud Rate
The baud rate is selected by the SF0BR9-0 bit of SF0BRR. This is only valid in Master mode. The baud-rate
clock SCKF0 is generated by dividing HSCLK or LSCLK.
The baud rate (f
SCK
) is calculated as follows.
f
SCK
=f
HLSCLK
/(2×SF0BR9-0)
f
SCK
: Frequency of baud-rate clock
f
HLSCLK
: Frequency of HSCLK or LSCLK
SF0BR : Value set in SF0BR9-0 of the SF0BRR register (1 to 1023)
If 0 is set the SF0BR register, it is processed as 1.
For SF0BR, it can be selected from 1023 dividing types (2 to 2046).
SF0CPHA=1
SINF0
SSF0
SCKF0
(SF0CPOL=0)
SCKF0
(SF0CPOL=1)
SOUTF0
Example for
SF0MOZ=SF0SOZ=SF0SSZ=SF0SIZ=SF0LSB=SF0LEAD=SF0LAG=0.
SCK Cycle