ML620Q503/Q504 User's Manual
Chapter 25 Successive Approximation Type A/D Converter
FEUL620Q504 25-14
25.3.2 Operation of the Successive Approximation Type A/D Converter
For direct input, operate SA-ADC in the following procedure.
(1) Normal mode
1.
Wait until the oscillation of the clock used for the A/D conversion is started and stabilized.
When LSCLK is selected, it is revealed that the oscillation is stabilized by the fact that T128HZ of the
low-speed time base counter register (LTBR) is set to “1”.
When OSCLK is selected and the high-speed crystal/ceramic oscillation mode, it is revealed that the
oscillation is stabilized by the fact that the HOSST bit of the FCON01 register is set to ”1”.
2.
Set the SA-ADC control register 0 (SADCON0), SA-ADC enable register (SADEN), and SA-ADC
accuracy control register (SADCVT).
3.
When the bit 2 (SATCM) of the SA-ADC control register 0 (SADCON0) is set to “0” then the bit 0
(SARUN) of the SA-ADC control register 1 (SADCON1) to “1”, the SA-ADC circuit starts operating to
perform A/D conversion on the channels selected in the SA-ADC enable register (SADEN) from a lower
channel number.
4.
A/D conversion results are stored in the applicable SA-ADC result registers (SADRn), and when A/D
conversion of the largest channel number is completed, a SA-ADC conversion termination interrupt
(SADINT) is generated.
(2) Trigger mode
1.
Wait until the oscillation of the clock used for the A/D conversion is started and stabilized.
When LSCLK is selected, it is revealed that the oscillation is stabilized by the fact that T128HZ of the
low-speed time base counter register (LTBR) is set to “1”.
When OSCLK is selected and the high-speed crystal/ceramic oscillation mode, it is revealed that the
oscillation is stabilized by the fact that the HOSST bit of the FCON01 register is set to ”1”.
2.
Set the SA-ADC control register 0 (SADCON0), SA-ADC enable register (SADEN), and SA-ADC
accuracy control register (SADCVT), where set SALP bit of SADCON0 register.
3
After trigger event source is selected by SA-ADC trigger register (SADTRG), and SAST0 bit is set to “1”,
the trigger mode is begun.
4.
If occur trigger event , the bit 0 (SARUN) of the SA-ADC control register 1 (SADCON1) to “1”, the
SA-ADC circuit starts operating to perform A/D conversion on the channels selected in the SA-ADC enable
register (SADEN) from a lower channel number.
5.
A/D conversion results are stored in the applicable SA-ADC result registers (SADRn), and when A/D
conversion of the largest channel number is completed, a SA-ADC conversion termination interrupt
(SADINT) is generated.
Even if the channel is switched during A/D conversion, it is held as selected at the start of A/D conversion until
an A/D conversion termination interrupt occurs.
Figure 25-3 shows the operation when channels 0 and 1 are selected.
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...