ML620Q503/Q504 User's Manual
Chapter 6 Clock Generation Circuit
FEUL620Q504
6–11
6.2.4
Frequency Status Register (FSTAT)
Address: 0F00AH
Access: R
Access size: 8 bits
Initial value: 06H
7
6
5
4
3
2
1
0
FSTAT
–
–
–
–
–
LOSCS
HOSCS
–
R/W
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
1
1
0
FSTAT is a special function register (SFR) used to show the clock generation circuit state.
Description of Bits
•
HOSCS
(bit 1)
HOSCS indicates the oscillation mode of the high-speed oscillator circuit. HOSCS changes when the
high-speed oscillation mode switches.
HOSCS is always "1" if the high-speed built-in RC oscillation mode is selected by the OSCM1 or
OSCM0 bit of the FCON0 register. Regardless of the high-speed oscillation mode, this becomes "1"
when the mode enters the STOP mode, DEEP-HALT mode, HALT-H mode.
HOSCS
Description
0
Operating in the high-speed crystal/ceramic oscillation mode or the external clock
input mode
1
•Operating with the high-speed built-in RC oscillator circuit (initial value)
•For the high-speed crystal/ceramic oscillation mode, the high-speed crystal/ceramic
oscillation has stopped or the stabilization time is being counted
•
LOSCS
(bit 2)
LOSCS indicates the oscillation mode of the low-speed oscillator circuit. LOSCS changes when the
low-speed oscillation mode switches. LOSCS is always "1" if the low-speed built-in RC oscillation mode
is selected by the XTM1 or XTM0 bit of the FCON2 register. Regardless of the low-speed oscillation
mode, this becomes "1" when the mode enters the STOP mode.
LOSCS
Description
0
Operating in the low-speed crystal oscillation mode or the external clock input mode
1
•Operating with the low-speed built-in RC oscillator circuit (initial value)
•For the low-speed crystal oscillation mode, the low-speed crystal oscillation has
stopped or the stabilization time is being counted
Summary of Contents for LAPIS SEMICONDUCTOR ML620Q503
Page 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Page 18: ...Chapter 1 Overview...
Page 32: ...Chapter 2 CPU and Memory Space...
Page 44: ...Chapter 3 Reset Function...
Page 50: ...Chapter 4 Power Management...
Page 70: ...Chapter 5 Interrupts...
Page 134: ...Chapter 6 Clock Generation Circuit...
Page 161: ...Chapter 7 Time Base Counter...
Page 170: ...Chapter 8 Timers...
Page 183: ...Chapter 9 Function Timer FTM...
Page 231: ...Chapter 10 Watchdog Timer...
Page 239: ...Chapter 11 Synchronous Serial Port SSIO...
Page 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Page 283: ...Chapter 13 UART...
Page 303: ...Chapter 14 UART with FIFO UARTF...
Page 327: ...Chapter 15 I2 C Bus Interface...
Page 344: ...Chapter 16 Port XT...
Page 350: ...Chapter 17 Port 0...
Page 361: ...Chapter 18 Port 1...
Page 368: ...Chapter 19 Port2...
Page 379: ...Chapter 20 Port 3...
Page 395: ...Chapter 21 Port 4...
Page 410: ...Chapter 22 Port 5...
Page 426: ...Chapter 23 Melody Driver...
Page 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Page 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Page 479: ...Chapter 26 Analog Comparator...
Page 489: ...Chapter 27 Flash Memory Control...
Page 505: ...Chapter 28 Voltage Level Supervisor VLS...
Page 517: ...Chapter 29 LLD circuit...
Page 519: ...Chapter 30 On Chip Debug Function...
Page 522: ...Appendixes...
Page 552: ...Revision History...