Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 4 Power Management
FEUL620Q504 4-13
4.3.1.3 HALT-H Mode
During the HALT-H mode, the CPU interrupts execution of instructions, the high-speed clock is stopped, and
only the peripheral circuits operate that can operate with the low-speed clock.
When the HLTH bit of the standby control register (SBYCON) is set to “1”, the mode changes to the HALT-H
mode.
When a WDT interrupt request, or an interrupt request enabled by an interrupt enable register (IE1 to IE7) is
issued, the HLTH bit is set to “0” on the falling edge of the next system clock (SYSCLK), the HALT-H mode is
released, and the mode returns to the program run mode.
When the HLTH bit is set to “1” during operation with the high-speed clock, the high-speed clock stops and the
mode changes to the HALT-H mode. If a WDT interrupt request, or an enabled interrupt request (the interrupt
enable flag is “1”) is issued in this state, HLTH is set to “0”, the high-speed clock restarts the operation, and the
mode returns to the program run mode.
About restart of a high-speed clock, it is same as DEEP-HALT.
Figure 4-4 shows the operation waveforms when the mode is changed to the HALT-H mode during the
high-speed clock operation.
SYSCLK
LSCLK
Program run mode HALT-H mode
Interrupt request
Program run mode
SBYCON.HLTH
HSCLK
Figure 4-4 Operation Waveforms in HALT-H Mode
[Note]
•When the mode switch to HALT-H mode at High speed oscillator is used,
Frequency Status Register (FSTAT) HOSCS bit must be “0”..
•After release of the HALT-H mode, interrupts other than WDT interrupt start being processed if they are
enabled (“1”) by the MIE bit of PSW.
For details of PSW, refer to “nX-U16/100 Core Instruction Manual”
•Since up to two instructions are executed during the period between HALT-H mode release and a transition
to interrupt processing, place two NOP instructions next to the instruction that sets the HLTH bit to “1”.