Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 6 Clock Generation Circuit
FEUL620Q504 6–21
6.3.2.5 High-Speed Crystal/Ceramic Oscillation Mode Operation
High speed clock is switch to crystal/ceramic oscillation mode by setting FCON0 bit of OSCM1,0 to “01”.
If the ENOSC bit of FCON1 is set to "1", the built-in RC oscillation clock is counted to 512 as the high-speed
clock, then the built-in RC oscillation clock is supplied as OSCLK. If the OSC1,0 bits of FCON0 are set to "01",
After waiting for the crystal/ceramic oscillation start time (T
XTH
) and the crystal/ceramic oscillation stabilization
time (4096 counts), the high-speed clock (OSCLK) switches from the built-in RC oscillation clock to the
crystal/ceramic oscillation clock.
In the case of low-speed crystal oscillation mode or external clock input mode, high-speed built-in oscillation
starts after the low-speed clock is counted to 26.
The high-speed clock generation circuit stops oscillation when it shifts to the STOP mode by software.
When the mode switch to STOP mode, FSTAT bit of HOSCS must be “0” and clock input from crystal/ceramic
oscillator must be stable.
By releasing the stop mode by an external interrupt, the low-speed built-in RC oscillation clock is counted to 29
and then the high-speed built-in RC oscillation clock is counted to 512, then the built-in RC oscillation clock is
supplied as OSCLK. After waiting for the crystal/ceramic oscillation start time (T
XTH
) and the crystal/ceramic
oscillation stabilization time (4096 counts), the high-speed clock (OSCLK) switches from the built-in RC
oscillation clock to the crystal/ceramic oscillation clock. Refer to Chapter 4 “Power Management” for the
operation at each power down mode.
Figure 6-13 shows the waveforms of the high-speed clock generation circuit in crystal/ceramic oscillation mode.