Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User’s Manual
Contents
FEUL620Q504 contents–6
12.3 Description of Operation
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12-
19
12.3.1 Master Mode and Slave Mode .............................................................................. 12-19
12.3.2 Control of Polarity and Phase of Serial Clock ...................................................... 12-19
12.3.3 Data Transfer Timing When SF0CPHA Is "0" ...................................................... 12-19
12.3.4 Data Transfer Timing When SF0CPHA Is "1" ...................................................... 12-20
12.3.5 Serial Clock Baud Rate ......................................................................................... 12-20
12.3.6 Transfer Size ......................................................................................................... 12-21
12.3.7 Transfer Interval Setting ....................................................................................... 12-22
12.3.8 Transmit Operation (Master Mode) ...................................................................... 12-24
12.3.9 Receive Operation (Master Mode) ....................................................................... 12-25
12.3.10 FIFO Operation ................................................................................................... 12-26
12.3.11 Write Overflow .................................................................................................... 12-26
12.3.12 Overrun Error ...................................................................................................... 12-26
12.3.13 FIFO Clearance .................................................................................................. 12-26
12.3.14 Transfer When Slave Has Different Number of FIFO Transfer Bytes/Words .... 12-27
12.3.15 Mode Fault (MDF) ............................................................................................... 12-28
12.3.16 Interrupt Source .................................................................................................. 12-29
12.3.16.1 SSIOF Interrupt Source
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12-
29
12.3.16.2 Clear SSIOF Interrupt
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12-
29
12.3.16.3 SSIOF Interrupt Timing
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12-
29
12.3.16.4 Interrupt processing flow
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12-
30
12.3.17 Hi-Z Operation .................................................................................................... 12-31
12.3.18 Interval from SF0MST Setting to Transfer Start ................................................. 12-31
12.3.19 Pin Settings ......................................................................................................... 12-31
Chapter 13
13. UART ............................................................................................................................................ 13-1
13.1 General Description
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13-
1
13.1.1 Features .................................................................................................................. 13-1
13.1.2 Configuration ........................................................................................................... 13-1
13.1.3 List of Pins .............................................................................................................. 13-2
13.2 Description of Registers .......................................................................................................... 13- 2
13.2.1 List of Registers ...................................................................................................... 13-2
13.2.2 UART0 Receive Buffer (UA0BUF) .......................................................................... 13-3
13.2.3 UART0 Transmit Buffer (UA1BUF) ......................................................................... 13-3
13.2.4 UART0 Control Register (UA0CON) ...................................................................... 13-4
13.2.5 UART0 Transmit Monitor Register (UA1CON) ....................................................... 13-5
13.2.6 UART0 Mode Register (UA0MOD) ......................................................................... 13-6
13.2.7 UART0 Baud Rate Registers (UA0BRT) ................................................................ 13-8
13.2.8 UART0 Receive Status Register (UA0STAT) ........................................................ 13-9
13.2.9 UART0 Transmit Status Register (UA1STAT) ..................................................... 13-10
13.3 Description of Operation ....................................................................................................... 13- 11
13.3.1 Transfer Data Format ........................................................................................... 13-11
13.3.2 Baud Rate ............................................................................................................. 13-12
13.3.3 Transmitted Data Direction ................................................................................... 13-13
13.3.4 Transmit Operation ............................................................................................... 13-14
13.3.5 Receive Operation ................................................................................................ 13-16
13.3.5.1 Detection of Start Bit
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13-
18
13.3.5.2 Sampling Timing
............................................................................................
13-
18
13.3.5.3 Receive Margin .............................................................................................. 13- 19