Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 15 I
2
C Bus Interface
FEUL620Q504 15–11
15.3 Description of Operation
15.3.1 Communication Operation Mode
Communication is started when communication mode is selected by using the I
2
C bus n mode register
(I2CnMOD), the I
2
C function is enabled by using the I2nEN bit, a slave address and a data communication
direction are set in the I
2
C bus n slave address register (I2CnSA), and “1” is written to the I2nST bit of the I
2
C
bus n control register (I2CnCON).
15.3.1.1 Start Condition
When “1” is written to the I2nST bit of the I
2
C bus n control register (I2CnCON) while communication is
stopped (the I2nST bit is “0”), communication is started and the start condition waveform is output to the SDA
and SCL pins.
After execution of the start condition, the LSI shifts to the slave address transmit mode.
15.3.1.2 Restart Condition
When “1” is written to the I2nRS and I2nST bits of the I
2
C bus n control register (I2CnCON) during
communication (the I2nST bit is “0”), the restart condition waveform is output to the SDA and SCL pins.
After execution of the restart condition, the LSI shifts to the slave address transmit mode.
15.3.1.3 Slave Address Transmit Mode
In slave address transmit mode, the values (slave address and data communication direction) of the I
2
C bus n
slave address register (I2CnSA) are transmitted in MSB first, and finally, the acknowledgment signal is received
in the I2nACR bit of the I
2
C bus n status register (I2CnSTAT).
At completion of acknowledgment reception, the LSI shifts to the I
2
C bus n control register (I2CnCON) setting
wait state (control register setting wait state).
The value of I2CnSA output from the SDA pin is stored in I2CnRD.
15.3.1.4 Data Transmit Mode
In data transmit mode, the value of I2CnTD is transmitted in MSB first, and finally, the acknowledgment signal is
received in the I2nACR bit of the I
2
C bus n status register (I2CnSTAT).
At completion of acknowledgment reception, the LSI shifts to the I
2
C bus n control register (I2CnCON) setting
wait state (control register setting wait state).
The value of I2CnTD output from the SDA pin is stored in I2CnRD.
15.3.1.5 Data receive mode
In data receive mode, the value input in the SDA pin is received synchronously with the rising edge of the serial
clock output to the SCL pin, and finally, the value of the I2nACT bit of the I
2
C bus n control register (I2CnCON)
is output.
At completion of acknowledgment transmission, the LSI shifts to the I
2
C bus n control register (I2CnCON)
setting wait state (control register setting wait state).
The data received is stored in I2CnRD after the acknowledgment signal is output. The acknowledgment signal
output is received in the I2nACR bit of the I
2
C bus n status register (I2CnSTAT).