Rohm LAPIS SEMICONDUCTOR ML620Q503, User Manual

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ML620Q503/Q504 User's Manual
Chapter 15 I
2
C Bus Interface
FEUL620Q504 15–1
15 I
2
C Bus Interface
15.1 General Description
The I
2
C bus interface operates as the master device of I
2
C bus and can communicate with the slave device.
This LSI includes two channels of I
2
C bus interface.
The I
2
C bus interface data I/O pin and the I
2
C bus interface clock I/O pin are assigned as the secondary function
of the ports 3, 4, and 5. For the ports 3, 4, and 5, see Chapter 20 “Port 3”, Chapter 21 “Port 4”, and Chapter 22
“Port 5”.
15.1.1 Features
•
Master function (Multi-master, stretch is not supported)
•
Communication speeds supported include standard mode (100kbps) and fast mode (400kbps).
•
7-bit address format (10-bit address can be supported)
15.1.2 Configuration
Figure 15-1 shows the configuration of the I
2
C bus interface.
I2CnRD : I
2
C bus n receive data register
I2CnSA : I
2
C bus n slave address register
I2CnTD : I
2
C bus n transmit data register
I2CnCON : I
2
C bus n control register
I2CnMOD : I
2
C bus n mode register
I2CnSTAT : I
2
C bus n status register
Figure 15-1 Configuration of I
2
C Bus Interface
15.1.3 List of Pins
Pin name I/O Function
SDAn I/O I
2
C bus interface data I/O pin
SCLn I/O I
2
C bus interface clock I/O pin
Clock
Generator
Shift Register
Data bus
I2C0INT,
I2C1INT
I2CnMOD
OSCLK
I2CnTD
I2CnRD, I2CnSTAT
SCL
SDA
Controller
I2CnCON
SCL0(P31/P41/P51)
SCL1(P35/P45/P55)
SDA0(P30/P40/P50)
SDA1(P34/P44/P54)
I2CnSA
I2C
Controller
n = 0,1